From: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Tue, 10 Oct 2017 17:41:02 +0000 (+0000)
Subject: fold-vec-cmp-char.c: New.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1e2a004031aa61ee6b8cef293c81942053953f4;p=gcc.git

fold-vec-cmp-char.c: New.

[testsuite]

2017-10-10  Will Schmidt <will_schmidt@vnet.ibm.com>
	* gcc.target/powerpc/fold-vec-cmp-char.c: New.
	* gcc.target/powerpc/fold-vec-cmp-double.c: New.
	* gcc.target/powerpc/fold-vec-cmp-float.c: New.
	* gcc.target/powerpc/fold-vec-cmp-int.c: New.
	* gcc.target/powerpc/fold-vec-cmp-longlong.c: New.
	* gcc.target/powerpc/fold-vec-cmp-short.c: New.

From-SVN: r253597
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ae985df7792..c2e064c7ff7 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2017-10-10  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+	* gcc.target/powerpc/fold-vec-splat-16.c: New
+	* gcc.target/powerpc/fold-vec-splat-32.c: New.
+	* gcc.target/powerpc/fold-vec-splat-8.c: New.
+
 2017-10-10  Thomas Koenig  <tkoenig@gcc.gnu.org>
 
 	PR libfortran/82233
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c
new file mode 100644
index 00000000000..3a1aa60cbff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.c
@@ -0,0 +1,86 @@
+/* Verify that overloaded built-ins for vec_cmp{eq,ge,gt,le,lt,ne} with
+   char inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector bool char
+test3_eq (vector signed char x, vector signed char y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool char
+test6_eq (vector unsigned char x, vector unsigned char y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool char
+test3_ge (vector signed char x, vector signed char y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool char
+test6_ge (vector unsigned char x, vector unsigned char y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool char
+test3_gt (vector signed char x, vector signed char y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool char
+test6_gt (vector unsigned char x, vector unsigned char y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool char
+test3_le (vector signed char x, vector signed char y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool char
+test6_le (vector unsigned char x, vector unsigned char y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool char
+test3_lt (vector signed char x, vector signed char y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool char
+test6_lt (vector unsigned char x, vector unsigned char y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool char
+test3_ne (vector signed char x, vector signed char y)
+{
+  return vec_cmpne (x, y);
+}
+
+vector bool char
+test6_ne (vector unsigned char x, vector unsigned char y)
+{
+  return vec_cmpne (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vcmpequb" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtsb" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtub" 4 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-double.c
new file mode 100644
index 00000000000..9d56862b2ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-double.c
@@ -0,0 +1,51 @@
+/* Verify that overloaded built-ins for vec_cmp with
+   double inputs for VSX produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector bool long long
+test2_eq (vector double x, vector double y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool long long
+test2_ge (vector double x, vector double y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool long long
+test2_gt (vector double x, vector double y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool long long
+test2_le (vector double x, vector double y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool long long
+test2_lt (vector double x, vector double y)
+{
+  return vec_cmplt (x, y);
+}
+
+	vector bool long long
+test2_ne (vector double x, vector double y)
+{
+  return vec_cmpne (x, y);
+}
+
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 2 } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 2 } } */
+/* { dg-final { scan-assembler-times "xvcmpnedp" 0 } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp" 2 } } */
+/* { dg-final { scan-assembler-times "fcmpu" 0 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-float.c
new file mode 100644
index 00000000000..b75250a7a3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-float.c
@@ -0,0 +1,51 @@
+/* Verify that overloaded built-ins for vec_cmp with float
+   inputs for VSX produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+vector bool int
+test1_eq (vector float x, vector float y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool int
+test1_ge (vector float x, vector float y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool int
+test1_gt (vector float x, vector float y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool int
+test1_le (vector float x, vector float y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool int
+test1_lt (vector float x, vector float y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool int
+test1_ne (vector float x, vector float y)
+{
+  return vec_cmpne (x, y);
+}
+
+/* { dg-final { scan-assembler-times "xvcmpeqsp" 2 } } */
+/* { dg-final { scan-assembler-times "xvcmpgtsp" 2 } } */
+/* { dg-final { scan-assembler-times "xvcmpnesp" 0 } } */
+/* { dg-final { scan-assembler-times "xvcmpgesp" 2 } } */
+/* { dg-final { scan-assembler-times "fcmpu" 0 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c
new file mode 100644
index 00000000000..d53994d3ac8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.c
@@ -0,0 +1,86 @@
+/* Verify that overloaded built-ins for vec_cmp with int
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector bool int
+test3_eq (vector signed int x, vector signed int y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool int
+test6_eq (vector unsigned int x, vector unsigned int y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool int
+test3_ge (vector signed int x, vector signed int y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool int
+test6_ge (vector unsigned int x, vector unsigned int y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool int
+test3_gt (vector signed int x, vector signed int y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool int
+test6_gt (vector unsigned int x, vector unsigned int y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool int
+test3_le (vector signed int x, vector signed int y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool int
+test6_le (vector unsigned int x, vector unsigned int y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool int
+test3_lt (vector signed int x, vector signed int y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool int
+test6_lt (vector unsigned int x, vector unsigned int y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool int
+test3_ne (vector signed int x, vector signed int y)
+{
+  return vec_cmpne (x, y);
+}
+
+vector bool int
+test6_ne (vector unsigned int x, vector unsigned int y)
+{
+  return vec_cmpne (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vcmpequw" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtsw" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtuw" 4 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c
new file mode 100644
index 00000000000..536ee75a854
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c
@@ -0,0 +1,86 @@
+/* Verify that overloaded built-ins for vec_cmp with long long
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector bool long long
+test3_eq (vector signed long long x, vector signed long long y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool long long
+test6_eq (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool long long
+test3_ge (vector signed long long x, vector signed long long y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool long long
+test6_ge (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool long long
+test3_gt (vector signed long long x, vector signed long long y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool long long
+test6_gt (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool long long
+test3_le (vector signed long long x, vector signed long long y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool long long
+test6_le (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool long long
+test3_lt (vector signed long long x, vector signed long long y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool long long
+test6_lt (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool long long
+test3_ne (vector signed long long x, vector signed long long y)
+{
+  return vec_cmpne (x, y);
+}
+
+vector bool long long
+test6_ne (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_cmpne (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vcmpequd" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtsd" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtud" 4 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c
new file mode 100644
index 00000000000..60676691efe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.c
@@ -0,0 +1,87 @@
+/* Verify that overloaded built-ins for vec_cmp with short
+   inputs produce the right code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector bool short
+test3_eq (vector signed short x, vector signed short y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool short
+test6_eq (vector unsigned short x, vector unsigned short y)
+{
+  return vec_cmpeq (x, y);
+}
+
+vector bool short
+test3_ge (vector signed short x, vector signed short y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool short
+test6_ge (vector unsigned short x, vector unsigned short y)
+{
+  return vec_cmpge (x, y);
+}
+
+vector bool short
+test3_gt (vector signed short x, vector signed short y)
+{
+  return vec_cmpgt (x, y);
+}
+
+vector bool short
+test6_gt (vector unsigned short x, vector unsigned short y)
+{
+  return vec_cmpgt (x, y);
+}
+
+
+vector bool short
+test3_le (vector signed short x, vector signed short y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool short
+test6_le (vector unsigned short x, vector unsigned short y)
+{
+  return vec_cmple (x, y);
+}
+
+vector bool short
+test3_lt (vector signed short x, vector signed short y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool short
+test6_lt (vector unsigned short x, vector unsigned short y)
+{
+  return vec_cmplt (x, y);
+}
+
+vector bool short
+test3_ne (vector signed short x, vector signed short y)
+{
+  return vec_cmpne (x, y);
+}
+
+vector bool short
+test6_ne (vector unsigned short x, vector unsigned short y)
+{
+  return vec_cmpne (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vcmpequh" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtsh" 4 } } */
+/* { dg-final { scan-assembler-times "vcmpgtuh" 4 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
+