From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 20:16:09 +0000 (+0100) Subject: whoops clk_sel_i renamed accidentally X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1eb3ba9e89bdb1748e6655cbe8342f4e0704cae;p=libresoc-litex.git whoops clk_sel_i renamed accidentally --- diff --git a/libresoc/core.py b/libresoc/core.py index c305d02..2035df2 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -273,7 +273,7 @@ class LibreSoC(CPU): self.pll_18_o = Signal() self.clk_sel = Signal(2) self.pll_ana_o = Signal() - self.cpu_params['i_clk__i'] = self.clk_sel + self.cpu_params['i_clk_sel_i'] = self.clk_sel self.cpu_params['o_pll_18_o'] = self.pll_18_o self.cpu_params['o_vco_test_ana_o'] = self.pll_ana_o