From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 14 Jan 2022 23:06:59 +0000 (-0800)
Subject: add grev[w][i][.] pseudo-code
X-Git-Tag: sv_maxu_works-initial~568
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1ec0f7f9f858a88d4ee66ae4df37dad600a6252;p=openpower-isa.git

add grev[w][i][.] pseudo-code
---

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index f428bd1b..1a0e9208 100644
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -18,3 +18,80 @@ Pseudo-code:
 Special Registers Altered:
 
     None
+
+# Generalized Bit-Reverse
+
+X-Form
+
+* grev RT, RA, RB (Rc=0)
+* grev. RT, RA, RB (Rc=1)
+
+Pseudo-code:
+
+    result <- [0] * XLEN
+    do i = 0 to XLEN - 1
+      idx <- ((RB) ^ i) % XLEN
+      result[i] <- (RA)[idx]
+    RT <- result
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+
+# Generalized Bit-Reverse Immediate
+
+XB-Form
+
+* grevi RT, RA, XBI (Rc=0)
+* grevi. RT, RA, XBI (Rc=1)
+
+Pseudo-code:
+
+    result <- [0] * XLEN
+    do i = 0 to XLEN - 1
+      idx <- (XBI ^ i) % XLEN
+      result[i] <- (RA)[idx]
+    RT <- result
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+# Generalized Bit-Reverse Word
+
+X-Form
+
+* grevw RT, RA, RB (Rc=0)
+* grevw. RT, RA, RB (Rc=1)
+
+Pseudo-code:
+
+    result <- [0] * XLEN # MSB half just stays zeroed
+    do i = 0 to XLEN / 2 - 1
+      idx <- ((RB) ^ i) % (XLEN / 2)
+      result[i] <- (RA)[idx]
+    RT <- result
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
+
+# Generalized Bit-Reverse Word Immediate
+
+X-Form
+
+* grevwi RT, RA, SH (Rc=0)
+* grevwi. RT, RA, SH (Rc=1)
+
+Pseudo-code:
+
+    result <- [0] * XLEN # MSB half just stays zeroed
+    do i = 0 to XLEN / 2 - 1
+      idx <- (SH ^ i) % (XLEN / 2)
+      result[i] <- (RA)[idx]
+    RT <- result
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)