From: Rafael Antognolli <rafael.antognolli@intel.com>
Date: Tue, 16 Apr 2019 13:31:06 +0000 (+0300)
Subject: intel/isl: Resize clear color buffer to full cacheline
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2041d2a9266ec14270b6da9bf9ce2b54d555ebd;p=mesa.git

intel/isl: Resize clear color buffer to full cacheline

Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI.

v2 (Nanley): In the title s/Align/Resize/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
---

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6b9e6c9e0f0..acfed5119ba 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -122,7 +122,8 @@ isl_device_init(struct isl_device *dev,
    dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
    dev->ss.align = isl_align(dev->ss.size, 32);
 
-   dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
+   dev->ss.clear_color_state_size =
+      isl_align(CLEAR_COLOR_length(info) * 4, 64);
    dev->ss.clear_color_state_offset =
       RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;