From: Richard Henderson Date: Wed, 13 Jun 2001 00:54:41 +0000 (-0700) Subject: i386.c (ix86_expand_prologue): Always use gen_pro_epilogue_adjust_stack; update argum... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2042df38f3451e2db4a84b26c9d46380bb91c26;p=gcc.git i386.c (ix86_expand_prologue): Always use gen_pro_epilogue_adjust_stack; update arguments. * config/i386/i386.c (ix86_expand_prologue): Always use gen_pro_epilogue_adjust_stack; update arguments. (ix86_expand_epilogue): Likewise. (ix86_emit_epilogue_esp_adjustment): Remove. (ix86_adjust_cost): Remove pro_epilogue_adjust_stack hack. * config/i386/i386.md (pro_epilogue_adjust_stack): Use a BLKmode clobber of scratch memory instead of a modification of EBP as the barrier. Update all peepholes to match. From-SVN: r43284 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3d24489c194..ea30da29afb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2001-06-12 Richard Henderson + + * config/i386/i386.c (ix86_expand_prologue): Always use + gen_pro_epilogue_adjust_stack; update arguments. + (ix86_expand_epilogue): Likewise. + (ix86_emit_epilogue_esp_adjustment): Remove. + (ix86_adjust_cost): Remove pro_epilogue_adjust_stack hack. + * config/i386/i386.md (pro_epilogue_adjust_stack): Use a BLKmode + clobber of scratch memory instead of a modification of EBP as the + barrier. Update all peepholes to match. + 2001-06-12 Joseph S. Myers * doc/gcc.texi: Change the font used for @def... commands to a @@ -132,18 +143,18 @@ Tue Jun 12 12:20:12 CEST 2001 Jan Hubicka * config/m32r/m32r.md (movstrsi_internal): Do not expect a return string from m32r_output_block_move. - * config/m32r/m32r-protos.h: Make m32r_output_block_move a + * config/m32r/m32r-protos.h: Make m32r_output_block_move a void function. - * config/m32r/m32r.h (INT32_P): Rename to UNIT32_P and remove + * config/m32r/m32r.h (INT32_P): Rename to UNIT32_P and remove integer overflow. - (ROUND_ADVANCE): Remove signed/unsigned conflict. - * config/m32r/m32r.c: Declare prototypes for static functions. - (move_src_operand): Replace INT32_P with UINT32_P. - (function_arg_partial_nregs): Fixed signed/unsigned conflict + (ROUND_ADVANCE): Remove signed/unsigned conflict. + * config/m32r/m32r.c: Declare prototypes for static functions. + (move_src_operand): Replace INT32_P with UINT32_P. + (function_arg_partial_nregs): Fixed signed/unsigned conflict in initialisation of 'size'. - (m32r_sched_reord): Remove redundant declarations of 'code'. - (m32r_output_block_move): Change to a void function. - (m32r_encode_section_info): Cast return of + (m32r_sched_reord): Remove redundant declarations of 'code'. + (m32r_output_block_move): Change to a void function. + (m32r_encode_section_info): Cast return of TREE_STRING_POINTER to avoid compile time warning. 2001-06-11 Richard Henderson diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 275788e48d4..cf60049447c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -561,7 +561,6 @@ static int ix86_safe_length_prefix PARAMS ((rtx)); static int ix86_nsaved_regs PARAMS((void)); static void ix86_emit_save_regs PARAMS((void)); static void ix86_emit_restore_regs_using_mov PARAMS ((rtx, int, int)); -static void ix86_emit_epilogue_esp_adjustment PARAMS((int)); static void ix86_set_move_mem_attrs_1 PARAMS ((rtx, rtx, rtx, rtx, rtx)); static void ix86_sched_reorder_pentium PARAMS((rtx *, rtx *)); static void ix86_sched_reorder_ppro PARAMS((rtx *, rtx *)); @@ -2497,17 +2496,9 @@ ix86_expand_prologue () ; else if (! TARGET_STACK_PROBE || frame.to_allocate < CHECK_STACK_LIMIT) { - if (frame_pointer_needed) - insn = emit_insn (gen_pro_epilogue_adjust_stack - (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (-frame.to_allocate), hard_frame_pointer_rtx)); - else - if (TARGET_64BIT) - insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (-frame.to_allocate))); - else - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (-frame.to_allocate))); + insn = emit_insn (gen_pro_epilogue_adjust_stack + (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (-frame.to_allocate))); RTX_FRAME_RELATED_P (insn) = 1; } else @@ -2545,28 +2536,6 @@ ix86_expand_prologue () emit_insn (gen_blockage ()); } -/* Emit code to add TSIZE to esp value. Use POP instruction when - profitable. */ - -static void -ix86_emit_epilogue_esp_adjustment (tsize) - int tsize; -{ - /* If a frame pointer is present, we must be sure to tie the sp - to the fp so that we don't mis-schedule. */ - if (frame_pointer_needed) - emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx, - stack_pointer_rtx, - GEN_INT (tsize), - hard_frame_pointer_rtx)); - else - if (TARGET_64BIT) - emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (tsize))); - else - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (tsize))); -} /* Emit code to restore saved registers using MOV insns. First register is restored from POINTER + OFFSET. */ @@ -2662,8 +2631,7 @@ ix86_expand_epilogue (style) emit_move_insn (hard_frame_pointer_rtx, tmp); emit_insn (gen_pro_epilogue_adjust_stack - (stack_pointer_rtx, sa, const0_rtx, - hard_frame_pointer_rtx)); + (stack_pointer_rtx, sa, const0_rtx)); } else { @@ -2674,8 +2642,10 @@ ix86_expand_epilogue (style) } } else if (!frame_pointer_needed) - ix86_emit_epilogue_esp_adjustment (frame.to_allocate - + frame.nregs * UNITS_PER_WORD); + emit_insn (gen_pro_epilogue_adjust_stack + (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (frame.to_allocate + + frame.nregs * UNITS_PER_WORD))); /* If not an i386, mov & pop is faster than "leave". */ else if (TARGET_USE_LEAVE || optimize_size) emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ()); @@ -2683,8 +2653,7 @@ ix86_expand_epilogue (style) { emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx, hard_frame_pointer_rtx, - const0_rtx, - hard_frame_pointer_rtx)); + const0_rtx)); if (TARGET_64BIT) emit_insn (gen_popdi1 (hard_frame_pointer_rtx)); else @@ -2701,11 +2670,12 @@ ix86_expand_epilogue (style) abort (); emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx, hard_frame_pointer_rtx, - GEN_INT (offset), - hard_frame_pointer_rtx)); + GEN_INT (offset))); } else if (frame.to_allocate) - ix86_emit_epilogue_esp_adjustment (frame.to_allocate); + emit_insn (gen_pro_epilogue_adjust_stack + (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (frame.to_allocate))); for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) if (ix86_save_reg (regno, false)) @@ -8308,14 +8278,6 @@ ix86_adjust_cost (insn, link, dep_insn, cost) insn_type = get_attr_type (insn); dep_insn_type = get_attr_type (dep_insn); - /* Prologue and epilogue allocators can have a false dependency on ebp. - This results in one cycle extra stall on Pentium prologue scheduling, - so handle this important case manually. */ - if (dep_insn_code_number == CODE_FOR_pro_epilogue_adjust_stack - && dep_insn_type == TYPE_ALU - && !reg_mentioned_p (stack_pointer_rtx, insn)) - return 0; - switch (ix86_cpu) { case PROCESSOR_PENTIUM: diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 015bd83be63..f06c0b04789 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1679,7 +1679,7 @@ (define_insn "*pushsi2_prologue" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_no_elim_operand" "ri*m")) - (set (reg:SI 6) (reg:SI 6))] + (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "push{l}\\t%1" [(set_attr "type" "push") @@ -1690,7 +1690,7 @@ (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) - (set (reg:SI 6) (reg:SI 6))] + (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "pop{l}\\t%0" [(set_attr "type" "pop") @@ -2413,7 +2413,7 @@ (define_insn "*pushdi2_prologue_rex64" [(set (match_operand:DI 0 "push_operand" "=<") (match_operand:DI 1 "general_no_elim_operand" "re*m")) - (set (reg:DI 6) (reg:DI 6))] + (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "push{q}\\t%1" [(set_attr "type" "push") @@ -2424,7 +2424,7 @@ (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) - (set (reg:DI 6) (reg:DI 6))] + (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "pop{q}\\t%0" [(set_attr "type" "pop") @@ -13621,7 +13621,8 @@ (define_insn "leave" [(set (reg:SI 7) (reg:SI 6)) - (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))] + (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7)))) + (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "leave" [(set_attr "length_immediate" "0") @@ -13633,7 +13634,8 @@ (define_insn "leave_rex64" [(set (reg:DI 7) (reg:DI 6)) - (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7))))] + (set (reg:DI 6) (mem:DI (pre_dec:DI (reg:DI 7)))) + (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "leave" [(set_attr "length_immediate" "0") @@ -16141,16 +16143,15 @@ [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "register_operand" "0,r") (match_operand:SI 2 "immediate_operand" "i,i"))) - (set (match_operand:SI 3 "register_operand" "+r,r") - (match_dup 3)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "" " { if (TARGET_64BIT) { - emit_insn (gen_pro_epilogue_adjust_stack_rex64 (operands[0], operands[1], - operands[2], operands[3])); + emit_insn (gen_pro_epilogue_adjust_stack_rex64 + (operands[0], operands[1], operands[2])); DONE; } }") @@ -16159,9 +16160,8 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "register_operand" "0,r") (match_operand:SI 2 "immediate_operand" "i,i"))) - (set (match_operand:SI 3 "register_operand" "+r,r") - (match_dup 3)) - (clobber (reg:CC 17))] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "* { @@ -16202,9 +16202,8 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (match_operand:DI 1 "register_operand" "0,r") (match_operand:DI 2 "x86_64_immediate_operand" "e,e"))) - (set (match_operand:DI 3 "register_operand" "+r,r") - (match_dup 3)) - (clobber (reg:CC 17))] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "* { @@ -17108,23 +17107,23 @@ (define_peephole2 [(match_scratch:SI 0 "r") (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) - (set (reg:SI 6) (reg:SI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_4" [(clobber (match_dup 0)) (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) - (set (reg:SI 6) (reg:SI 6))])]) + (clobber (mem:BLK (scratch)))])]) (define_peephole2 [(match_scratch:SI 0 "r") (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) - (set (reg:SI 6) (reg:SI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_8" [(clobber (match_dup 0)) (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) - (set (reg:SI 6) (reg:SI 6))])]) + (clobber (mem:BLK (scratch)))])]) ;; Convert esp substractions to push. (define_peephole2 @@ -17148,12 +17147,12 @@ (define_peephole2 [(match_scratch:SI 0 "r") (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) - (set (reg:SI 6) (reg:SI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_4" [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) - (set (reg:SI 6) (reg:SI 6))])] + (clobber (mem:BLK (scratch)))])] "") ;; Two pops case is tricky, since pop causes dependency on destination register. @@ -17162,12 +17161,12 @@ [(match_scratch:SI 0 "r") (match_scratch:SI 1 "r") (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) - (set (reg:SI 6) (reg:SI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_8" [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) - (set (reg:SI 6) (reg:SI 6))]) + (clobber (mem:BLK (scratch)))]) (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] "") @@ -17175,12 +17174,12 @@ (define_peephole2 [(match_scratch:SI 0 "r") (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) - (set (reg:SI 6) (reg:SI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size" [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) - (set (reg:SI 6) (reg:SI 6))]) + (clobber (mem:BLK (scratch)))]) (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] "") @@ -17286,23 +17285,23 @@ (define_peephole2 [(match_scratch:DI 0 "r") (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) - (set (reg:DI 6) (reg:DI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_4" [(clobber (match_dup 0)) (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) - (set (reg:DI 6) (reg:DI 6))])]) + (clobber (mem:BLK (scratch)))])]) (define_peephole2 [(match_scratch:DI 0 "r") (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) - (set (reg:DI 6) (reg:DI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_8" [(clobber (match_dup 0)) (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) - (set (reg:DI 6) (reg:DI 6))])]) + (clobber (mem:BLK (scratch)))])]) ;; Convert esp substractions to push. (define_peephole2 @@ -17326,12 +17325,12 @@ (define_peephole2 [(match_scratch:DI 0 "r") (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) - (set (reg:DI 6) (reg:DI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_4" [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) - (set (reg:DI 6) (reg:DI 6))])] + (clobber (mem:BLK (scratch)))])] "") ;; Two pops case is tricky, since pop causes dependency on destination register. @@ -17340,12 +17339,12 @@ [(match_scratch:DI 0 "r") (match_scratch:DI 1 "r") (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) - (set (reg:DI 6) (reg:DI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_8" [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) - (set (reg:DI 6) (reg:DI 6))]) + (clobber (mem:BLK (scratch)))]) (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] "") @@ -17353,12 +17352,12 @@ (define_peephole2 [(match_scratch:DI 0 "r") (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) - (set (reg:DI 6) (reg:DI 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC 17)) + (clobber (mem:BLK (scratch)))])] "optimize_size" [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) - (set (reg:DI 6) (reg:DI 6))]) + (clobber (mem:BLK (scratch)))]) (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] "")