From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 18:01:46 +0000 (-0700)
Subject: synth_xilinx with abc9 to use -box
X-Git-Tag: working-ls180~1208^2~374
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2042fc7c43af9f43d42fdd2e8034963122ff5eb;p=yosys.git

synth_xilinx with abc9 to use -box
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 090bcce85..eb37feb83 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -275,7 +275,10 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
-			Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+			if (abc == "abc9")
+				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
+			else
+				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 		}