From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 12:02:22 +0000 (+0100)
Subject: whoops missed set up of temp variable bw
X-Git-Tag: ls180-24jan2020~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f20620360b62b6ab4ad2c67d7537b430161ce957;p=ieee754fpu.git

whoops missed set up of temp variable bw
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index a6a65cc8..c4076266 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -224,6 +224,7 @@ class DivPipeCoreSetupStage(Elaboratable):
         self.core_config = core_config
         self.i = self.ispec()
         self.o = self.ospec()
+        bw = core_config.bit_width
         if core_config.supported == [DP.UDivRem]:
             self.compare_len = bw * 2
         else: