From: Luke Kenneth Casson Leighton Date: Mon, 26 Nov 2018 07:41:29 +0000 (+0000) Subject: complete csrs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f21222df4fd037f0cc6ef11096d4eebb9ee0633d;p=rv32.git complete csrs --- diff --git a/cpu.py b/cpu.py index b5f863c..9b36071 100644 --- a/cpu.py +++ b/cpu.py @@ -107,6 +107,7 @@ class MIE: self.meie = Signal(name="mie_meie") self.mtie = Signal(name="mie_mtie") self.msie = Signal(name="mie_msie") + self.seie = Signal(name="mie_seie") self.ueie = Signal(name="mie_ueie") self.stie = Signal(name="mie_stie") self.utie = Signal(name="mie_utie") @@ -122,6 +123,12 @@ class MIE: self.sync += self.mtie.eq(0) self.sync += self.msie.eq(0) + def make(self): + return Cat( self.usie, self.ssie, 0, self.msie, + self.utie, self.stie, 0, self.mtie, + self.ueie, self.seie, 0, self.meie, ) + + class MIP: def __init__(self, comb, sync): self.comb = comb @@ -137,10 +144,15 @@ class MIP: self.usip = Signal(name="mip_usip") for n in dir(self): - if n in ['comb', 'sync'] or n.startswith("_"): + if n in ['make', 'comb', 'sync'] or n.startswith("_"): continue self.comb += getattr(self, n).eq(0x0) + def make(self): + return Cat( self.usip, self.ssip, 0, self.msip, + self.utip, self.stip, 0, self.mtip, + self.ueip, self.seip, 0, self.meip, ) + class M: def __init__(self, comb, sync): @@ -400,7 +412,8 @@ class CPU(Module): s.append(i) return s - def main_block(self, minfo, misa, csr, mi, m, mstatus, ft, dc, + def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie, + ft, dc, load_store_misaligned, loaded_value, alu_result, lui_auipc_result): @@ -408,14 +421,16 @@ class CPU(Module): c[FOS.empty] = [] c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc, load_store_misaligned) - c[FOS.valid] = self.handle_valid(minfo, misa, csr, mi, m, mstatus, ft, dc, + c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m, + mstatus, mie, ft, dc, load_store_misaligned, loaded_value, alu_result, lui_auipc_result) return Case(ft.output_state, c) - def handle_valid(self, minfo, misa, csr, mi, m, mstatus, ft, dc, + def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie, + ft, dc, load_store_misaligned, loaded_value, alu_result, lui_auipc_result): @@ -448,7 +463,8 @@ class CPU(Module): ) i = i.Elif((dc.act & DA.csr) != 0, - self.handle_csr(minfo, misa, mstatus, dc, csr) + self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m, + dc, csr) ) # fence, store, branch @@ -459,7 +475,7 @@ class CPU(Module): return i - def handle_csr(self, minfo, misa, mstatus, dc, csr): + def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr): csr_output_value = Signal(32) csr_written_value = Signal(32) c = {} @@ -483,11 +499,57 @@ class CPU(Module): # mstatus c[csr_mstatus ] = [ csr_output_value.eq(mstatus.make()), - csr.evaluate_csr_funct3_op(dc.funct3, csr_written_value, - csr_output_value), + csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, + csr_written_value), mstatus.mpie.eq(csr_written_value[7]), mstatus.mie.eq(csr_written_value[3]) ] + # mie + c[csr_mie ] = [ + csr_output_value.eq(mie.make()), + csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, + csr_written_value), + mie.meie.eq(csr_written_value[11]), + mie.mtie.eq(csr_written_value[7]), + mie.msie.eq(csr_written_value[3]), + ] + # mtvec + c[csr_mtvec ] = csr_output_value.eq(mtvec) + # mscratch + c[csr_mscratch ] = [ + csr_output_value.eq(m.mscratch), + csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, + csr_written_value), + If(csr.writes, + m.mscratch.eq(csr_written_value), + ) + ] + # mepc + c[csr_mepc ] = [ + csr_output_value.eq(m.mepc), + csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, + csr_written_value), + If(csr.writes, + m.mepc.eq(csr_written_value), + ) + ] + + # mcause + c[csr_mcause ] = [ + csr_output_value.eq(m.mcause), + csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, + csr_written_value), + If(csr.writes, + m.mcause.eq(csr_written_value), + ) + ] + + # mip + c[csr_mip ] = [ + csr_output_value.eq(mip.make()), + csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, + csr_written_value), + ] return [Case(csr.number, c), If(csr.reads, @@ -495,45 +557,6 @@ class CPU(Module): )] """ - `csr_mie: begin - csr_output_value = 0; - csr_output_value[11] = mie_meie; - csr_output_value[9] = mie_seie; - csr_output_value[8] = mie_ueie; - csr_output_value[7] = mie_mtie; - csr_output_value[5] = mie_stie; - csr_output_value[4] = mie_utie; - csr_output_value[3] = mie_msie; - csr_output_value[1] = mie_ssie; - csr_output_value[0] = mie_usie; - csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); - if(csr_writes) begin - mie_meie = csr_written_value[11]; - mie_mtie = csr_written_value[7]; - mie_msie = csr_written_value[3]; - end - end - `csr_mtvec: begin - csr_output_value = mtvec; - end - `csr_mscratch: begin - csr_output_value = mscratch; - csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); - if(csr_writes) - mscratch = csr_written_value; - end - `csr_mepc: begin - csr_output_value = mepc; - csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); - if(csr_writes) - mepc = csr_written_value; - end - `csr_mcause: begin - csr_output_value = mcause; - csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); - if(csr_writes) - mcause = csr_written_value; - end `csr_mip: begin csr_output_value = 0; csr_output_value[11] = mip_meip; @@ -547,9 +570,6 @@ class CPU(Module): csr_output_value[0] = mip_usip; end endcase - if(csr_reads) - write_register(decoder_rd, csr_output_value); - end end endcase end @@ -791,8 +811,8 @@ class CPU(Module): minfo = MInfo(self.comb) self.sync += If(~self.reset, - self.main_block(minfo, misa, csr, mi, m, - mstatus, ft, dc, + self.main_block(mtvec, mip, minfo, misa, csr, mi, m, + mstatus, mie, ft, dc, load_store_misaligned, loaded_value, alu_result,