From: lkcl <lkcl@web>
Date: Sun, 4 Sep 2022 19:46:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~698
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f21a6019bab62c8d1e97432753fa24d2f5284721;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 7f08c1b9a..dec1ff763 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -588,10 +588,14 @@ If EXTRA2 is zero will map to
 | 10       | Vector | `r0-r124`/4 | `RA 0b00`      |
 | 11       | Vector | `r2-r126`/4 | `RA 0b10`   |
 
+Note that unlike in EXTRA3, in EXTRA2 the GPR Vectors may only start from
+`r0, r2, r4, r6, r8` and likewise FPR Vectors as there is insufficient
+bits to cover the full range.
+
 ## CR Field EXTRA3
 
 CR Field encoding is essentially the same but made more complex due to CRs being bit-based.  See [[svp64/appendix]] for explanation and pseudocode.
-Note that Vectors may only start from CR0, CR4, CR8, CR12, CR16...
+Note that Vectors may only start from `CR0, CR4, CR8, CR12, CR16`...
 
 Encoding shown MSB down to LSB