From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 23 Feb 2022 13:14:52 +0000 (+0000)
Subject: add comments about DRAM sync clock being identical to main clock
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2357f22dc48692756118a52b9ce3ae5171a07ca;p=ls2.git

add comments about DRAM sync clock being identical to main clock
---

diff --git a/src/crg.py b/src/crg.py
index 3cf483f..6fb8dd1 100644
--- a/src/crg.py
+++ b/src/crg.py
@@ -236,6 +236,8 @@ class ECPIX5CRG(Elaboratable):
             i_CLKI=ClockSignal("sync2x"),
             i_RST=0,
             o_CDIVX=ClockSignal("sync"))
+
+        # temporarily set dram sync clock exactly equal to main sync
         m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
 
         return m