From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Mon, 20 Apr 2020 04:46:09 +0000 (+0000)
Subject: Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
X-Git-Tag: working-ls180~517^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f235f212ea242d765e38f4b317390657c1291f77;p=yosys.git

Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 17d98847e..ab719cbaa 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -490,8 +490,8 @@ struct TechmapWorker
 		}
 
 		TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
-		dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
-		dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
+		dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
+		dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
 
 		for (auto cell : module->selected_cells())
 		{