From: Luke Kenneth Casson Leighton Date: Thu, 16 Dec 2021 17:07:58 +0000 (+0000) Subject: whoops, a Simulation bug, dcache bus ack Signal needed to be X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f23716a9508b6696b6633083f9bb2c4353613c30;p=soc.git whoops, a Simulation bug, dcache bus ack Signal needed to be copied into a separate combinatorial Signal --- diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index abef5d6d..1a34aa2c 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1529,8 +1529,10 @@ class DCache(Elaboratable): sync += r1.wb.adr[:LINE_OFF_BITS-ROW_OFF_BITS].eq(row+1) # Incoming acks processing - sync += r1.forward_valid1.eq(bus.ack) - with m.If(bus.ack): + bus_ack = Signal() + comb += bus_ack.eq(bus.ack) # o dear - Simulation bug.... + sync += r1.forward_valid1.eq(bus_ack) + with m.If(bus_ack): srow = Signal(ROW_LINE_BITS) comb += srow.eq(r1.store_row) sync += r1.rows_valid[srow].eq(1)