From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Mar 2019 21:54:43 +0000 (-0700)
Subject: Fix INIT for variable length SRs that have been bumped up one
X-Git-Tag: yosys-0.9~171^2~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f239cb821edb86c3ec48782139e982819f073a7c;p=yosys.git

Fix INIT for variable length SRs that have been bumped up one
---

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 1d538e262..94a48dbc2 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -106,7 +106,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
       else begin
         // For variable length, bump up to the next length
         // because we can't access Q31
-        \$__SHREG_ #(.DEPTH(DEPTH+1), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
+        \$__SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
       end
     end 
     else begin