From: Florent Kermarrec Date: Sat, 27 Sep 2014 14:22:40 +0000 (+0200) Subject: mmcm: configure default divider with default_speed X-Git-Tag: 24jan2021_ls180~2572^2~189 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f23c5aa724fa545c4dc900a3cedfd827ccda960b;p=litex.git mmcm: configure default divider with default_speed --- diff --git a/lib/sata/k7sataphy/__init__.py b/lib/sata/k7sataphy/__init__.py index 8bcd029b..92343247 100644 --- a/lib/sata/k7sataphy/__init__.py +++ b/lib/sata/k7sataphy/__init__.py @@ -9,12 +9,12 @@ from lib.sata.k7sataphy.datapath import K7SATAPHYRXAlign from lib.sata.k7sataphy.datapath import K7SATAPHYRXConvert, K7SATAPHYTXConvert class K7SATAPHY(Module): - def __init__(self, pads, clk_freq, host=True,): + def __init__(self, pads, clk_freq, host=True, default_speed="SATA3"): self.sink = Sink([("d", 32)], True) self.source = Source([("d", 32)], True) # GTX - gtx = K7SATAPHYGTX(pads, "SATA3") + gtx = K7SATAPHYGTX(pads, default_speed) self.comb += [ gtx.rxrate.eq(0b000), gtx.txrate.eq(0b000), @@ -22,7 +22,7 @@ class K7SATAPHY(Module): self.submodules += gtx # CRG / CTRL - crg = K7SATAPHYCRG(pads, gtx, clk_freq) + crg = K7SATAPHYCRG(pads, gtx, clk_freq, default_speed) if host: ctrl = K7SATAPHYHostCtrl(gtx) else: diff --git a/lib/sata/k7sataphy/crg.py b/lib/sata/k7sataphy/crg.py index 82ac4f7e..732ace4f 100644 --- a/lib/sata/k7sataphy/crg.py +++ b/lib/sata/k7sataphy/crg.py @@ -25,7 +25,7 @@ class K7SATAPHYReconfig(Module): ) class K7SATAPHYCRG(Module): - def __init__(self, pads, gtx, clk_freq): + def __init__(self, pads, gtx, clk_freq, default_speed): self.reset = Signal() self.ready = Signal() @@ -59,6 +59,12 @@ class K7SATAPHYCRG(Module): mmcm_clk_i = Signal() mmcm_clk0_o = Signal() mmcm_clk1_o = Signal() + mmcm_div_config = { + "SATA1" : 16, + "SATA2" : 8, + "SATA3" : 4 + } + mmcm_div = mmcm_div_config[default_speed] self.specials += [ Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i), Instance("MMCME2_ADV", @@ -74,10 +80,10 @@ class K7SATAPHYCRG(Module): i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb, # CLK0 - p_CLKOUT0_DIVIDE_F=4.000, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o, + p_CLKOUT0_DIVIDE_F=mmcm_div, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o, # CLK1 - p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o, + p_CLKOUT1_DIVIDE=mmcm_div*2, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o, ), Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk), ] diff --git a/lib/sata/k7sataphy/gtx.py b/lib/sata/k7sataphy/gtx.py index f0baf42b..118a5647 100644 --- a/lib/sata/k7sataphy/gtx.py +++ b/lib/sata/k7sataphy/gtx.py @@ -6,7 +6,7 @@ from migen.flow.actor import Sink, Source from lib.sata.k7sataphy.std import * class K7SATAPHYGTX(Module): - def __init__(self, pads, default_speed="SATA3"): + def __init__(self, pads, default_speed): self.drp = DRPBus() # Channel - Ref Clock Ports