From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 18 Oct 2018 08:58:47 +0000 (+0200)
Subject: Merge pull request #659 from rubund/sv_interfaces
X-Git-Tag: yosys-0.9~440
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c;p=yosys.git

Merge pull request #659 from rubund/sv_interfaces

Support for SystemVerilog interfaces and modports
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f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c