From: Luke Kenneth Casson Leighton Date: Wed, 3 Jun 2020 02:01:50 +0000 (+0100) Subject: tidyup branch. comments X-Git-Tag: div_pipeline~637^2~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f254d5500eda9028cfad1cef910272ba2d22aa78;p=soc.git tidyup branch. comments --- diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py index 0e9e7f57..27076a56 100644 --- a/src/soc/fu/branch/main_stage.py +++ b/src/soc/fu/branch/main_stage.py @@ -76,18 +76,17 @@ class BranchMainStage(PipeModBase): comb += br_addr.eq(br_imm_addr + cia) # fields for conditional branches (BO and BI are same for BC and BCREG) - # NOTE: here, BO and BI we would like be treated as CR regfile - # selectors (similar to RA, RB, RS, RT). see comment here: - # https://bugs.libre-soc.org/show_bug.cgi?id=313#c2 b_fields = self.fields.FormB BO = b_fields.BO[0:-1] - BI = b_fields.BI[0:-1][0:2] + BI = b_fields.BI[0:-1][0:2] # CR0-7 selected already in PowerDecode2. - cr_bits = Array([cr[3-i] for i in range(4)]) + cr_bits = Array([cr[3-i] for i in range(4)]) # invert. Because POWER. # The bit of CR selected by BI + bi = Signal(2, reset_less=True) cr_bit = Signal(reset_less=True) - comb += cr_bit.eq(cr_bits[BI]) + comb += bi.eq(BI) # reduces gate-count due to pmux + comb += cr_bit.eq(cr_bits[bi]) # Whether ctr is written to on a conditional branch ctr_write = Signal(reset_less=True)