From: Kenneth Graunke Date: Thu, 16 Nov 2017 07:06:27 +0000 (-0800) Subject: genxml: Fix PIPELINE_SELECT on G45/Ironlake. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f274687413cadb5f7cf2242f85e27c11c5753dfa;p=mesa.git genxml: Fix PIPELINE_SELECT on G45/Ironlake. Original 965 sets bits 28:27 to 0, while G45 and later set it to 1. Note that the G45 docs are incorrect in this regard - see the DevCTG+ note in the Ironlake PRMs. Reviewed-by: Lionel Landwerlin --- diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml index c91085831ea..136cc6f68a3 100644 --- a/src/intel/genxml/gen45.xml +++ b/src/intel/genxml/gen45.xml @@ -1162,7 +1162,7 @@ - + diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml index 93e687a32bd..82cda909572 100644 --- a/src/intel/genxml/gen5.xml +++ b/src/intel/genxml/gen5.xml @@ -1253,7 +1253,7 @@ - +