From: Michael Meissner Date: Thu, 3 Nov 2016 23:32:07 +0000 (+0000) Subject: re PR target/78192 (extract from vector registers to int results in wrong data order) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2834ebc00d847dcac85c44640a2c7fb2cdd340e;p=gcc.git re PR target/78192 (extract from vector registers to int results in wrong data order) 2016-11-03 Michael Meissner PR target/78192 * config/rs6000/vsx.md (vsx_extract__di): The element number has already been adjusted for endianness, so don't adjust it any further. From-SVN: r241834 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b45b91ddfdb..9222baaa498 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2016-11-03 Michael Meissner + PR target/78192 + * config/rs6000/vsx.md (vsx_extract__di): The element number + has already been adjusted for endianness, so don't adjust it any + further. + PR target/77993 * config/rs6000/rs6000.h (FLOAT128_IBM_P): Do not allow IFmode or ICmode unless we have standard PowerPC floating point. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 505c270edfd..2c74a8ebbe2 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2586,11 +2586,10 @@ (parallel [(match_operand:QI 2 "" "n")]))))] "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB" { - int element = INTVAL (operands[2]); + /* Note, the element number has already been adjusted for endianness, so we + don't have to adjust it here. */ int unit_size = GET_MODE_UNIT_SIZE (mode); - int offset = ((VECTOR_ELT_ORDER_BIG) - ? unit_size * element - : unit_size * (GET_MODE_NUNITS (mode) - 1 - element)); + HOST_WIDE_INT offset = unit_size * INTVAL (operands[2]); operands[2] = GEN_INT (offset); if (unit_size == 4)