From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Sun, 13 Sep 2020 11:44:18 +0000 (+0100)
Subject: arch-riscv: Replace any getDTBPtr/getITBPtr usage
X-Git-Tag: develop-gem5-snapshot~557
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f28b2e773f2ee97bf9c755b33aef9befc052d281;p=gem5.git

arch-riscv: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34980
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index b39005ff3..5ef68fe1f 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1848,8 +1848,7 @@ decode QUADRANT default Unknown::unknown() {
                                         "sfence in user mode or TVM enabled",
                                         machInst);
                         }
-                        xc->tcBase()->getITBPtr()->demapPage(Rs1, Rs2);
-                        xc->tcBase()->getDTBPtr()->demapPage(Rs1, Rs2);
+                        xc->tcBase()->getMMUPtr()->demapPage(Rs1, Rs2);
                     }}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
                     0x18: mret({{
                         if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index 16114c95b..009f1434d 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -61,7 +61,7 @@ output decoder {{
 
 #include "arch/riscv/decoder.hh"
 #include "arch/riscv/faults.hh"
-#include "arch/riscv/tlb.hh"
+#include "arch/riscv/mmu.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
@@ -81,6 +81,7 @@ output exec {{
 
 #include "arch/generic/memhelpers.hh"
 #include "arch/riscv/faults.hh"
+#include "arch/riscv/mmu.hh"
 #include "arch/riscv/registers.hh"
 #include "arch/riscv/utility.hh"
 #include "base/condcodes.hh"
diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh
index d10ce137a..322f0afb8 100644
--- a/src/arch/riscv/mmu.hh
+++ b/src/arch/riscv/mmu.hh
@@ -39,6 +39,8 @@
 #define __ARCH_RISCV_MMU_HH__
 
 #include "arch/generic/mmu.hh"
+#include "arch/riscv/isa.hh"
+#include "arch/riscv/tlb.hh"
 
 #include "params/RiscvMMU.hh"
 
@@ -50,6 +52,18 @@ class MMU : public BaseMMU
     MMU(const RiscvMMUParams &p)
       : BaseMMU(p)
     {}
+
+    PrivilegeMode
+    getMemPriv(ThreadContext *tc, BaseTLB::Mode mode)
+    {
+        return static_cast<TLB*>(dtb)->getMemPriv(tc, mode);
+    }
+
+    Walker *
+    getDataWalker()
+    {
+        return static_cast<TLB*>(dtb)->getWalker();
+    }
 };
 
 } // namespace RiscvISA
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 7da666d2e..0e4c544ba 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -134,9 +134,9 @@
 
 #include <string>
 
+#include "arch/riscv/mmu.hh"
 #include "arch/riscv/pagetable_walker.hh"
 #include "arch/riscv/registers.hh"
-#include "arch/riscv/tlb.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "mem/page_table.hh"
@@ -155,15 +155,15 @@ RemoteGDB::acc(Addr va, size_t len)
 {
     if (FullSystem)
     {
-        TLB *tlb = dynamic_cast<TLB *>(context()->getDTBPtr());
+        MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
         unsigned logBytes;
         Addr paddr = va;
 
-        PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+        PrivilegeMode pmode = mmu->getMemPriv(context(), BaseTLB::Read);
         SATP satp = context()->readMiscReg(MISCREG_SATP);
         if (pmode != PrivilegeMode::PRV_M &&
             satp.mode != AddrXlateMode::BARE) {
-            Walker *walker = tlb->getWalker();
+            Walker *walker = mmu->getDataWalker();
             Fault fault = walker->startFunctional(
                     context(), paddr, logBytes, BaseTLB::Read);
             if (fault != NoFault)
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 883a6ca51..62517e90c 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -35,6 +35,7 @@
 
 #include "arch/riscv/faults.hh"
 #include "arch/riscv/fs_workload.hh"
+#include "arch/riscv/mmu.hh"
 #include "arch/riscv/pagetable.hh"
 #include "arch/riscv/pagetable_walker.hh"
 #include "arch/riscv/pra_constants.hh"
@@ -411,13 +412,13 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
     Addr paddr = vaddr;
 
     if (FullSystem) {
-        TLB *tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
+        MMU *mmu = static_cast<MMU *>(tc->getMMUPtr());
 
-        PrivilegeMode pmode = tlb->getMemPriv(tc, mode);
+        PrivilegeMode pmode = mmu->getMemPriv(tc, mode);
         SATP satp = tc->readMiscReg(MISCREG_SATP);
         if (pmode != PrivilegeMode::PRV_M &&
             satp.mode != AddrXlateMode::BARE) {
-            Walker *walker = tlb->getWalker();
+            Walker *walker = mmu->getDataWalker();
             unsigned logBytes;
             Fault fault = walker->startFunctional(
                     tc, paddr, logBytes, mode);