From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jun 2020 23:48:01 +0000 (+0100)
Subject: whitespace
X-Git-Tag: div_pipeline~404
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f28cca6470be176d84d69f83950a46268e0f3a1c;p=soc.git

whitespace
---

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index fdc9c323..a88375d0 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -16,7 +16,8 @@ name, return a tuple of:
 Note that some of the port numbering encoding is *unary*.  in the case
 of "Full Condition Register", it's a full 8-bit mask of read/write-enables.
 This actually matches directly with the XFX field in MTCR, and at
-some point that 8-bit mask from the instruction could actually be passed        directly through to full_cr (TODO).
+some point that 8-bit mask from the instruction could actually be passed
+directly through to full_cr (TODO).
 
 For the INT and CR numbering, these are expressed in binary in the
 instruction (note however that XFX in MTCR is unary-masked!)
diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 851bc858..630dc9b8 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -330,7 +330,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # dest operand latch
         comb += wri_l.s.eq(issue_i)
-        sync += wri_l.r.eq(reset_w)
+        sync += wri_l.r.eq(reset_w | Repl(self.done_o, self.n_dst))
 
         # update-mode operand latch (EA written to reg 2)
         sync += upd_l.s.eq(reset_i)
@@ -338,7 +338,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
 
         # store latch
         comb += sto_l.s.eq(addr_ok & op_is_st)
-        comb += sto_l.r.eq(reset_s)
+        sync += sto_l.r.eq(reset_s)
 
         # reset latch
         comb += rst_l.s.eq(addr_ok) # start when address is ready
@@ -413,15 +413,15 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 
         # address release only if addr ready, but Port must be idle
-        comb += self.adr_rel_o.eq(adr_l.q & busy_o)
+        comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
 
         # store release when st ready *and* all operands read (and no shadow)
         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
                                self.shadown_i)
 
         # request write of LD result.  waits until shadow is dropped.
-        comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
-                                  self.shadown_i)
+        comb += self.wr.rel[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
+                                  op_is_ld & self.shadown_i)
 
         # request write of EA result only in update mode
         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 971e46a8..a62a4694 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -56,6 +56,7 @@ def get_cu_output(cu, idx, code):
     yield
     yield cu.wr.go[idx].eq(0)
     print ("result", repr(code), idx, wrop, wrok, hex(result))
+
     return result
 
 
@@ -198,12 +199,12 @@ class TestRunner(FHDLTestCase):
                     wr_rel_o = yield cu.wr.rel
                     print ("before inputs, rd_rel, wr_rel: ",
                             bin(rd_rel_o), bin(wr_rel_o))
+                    yield
                     assert wr_rel_o == 0, "wr.rel %s must be zero. "\
                                 "previous instr not written all regs\n"\
                                 "respec %s" % \
                                 (bin(wr_rel_o), cu.rwid[1])
                     yield from set_cu_inputs(cu, inp)
-                    yield
                     rd_rel_o = yield cu.rd.rel
                     wr_rel_o = yield cu.wr.rel
                     wrmask = yield cu.wrmask
@@ -219,6 +220,14 @@ class TestRunner(FHDLTestCase):
                     # get all outputs (one by one, just "because")
                     res = yield from get_cu_outputs(cu, code)
 
+                    # wait for busy to go low
+                    while True:
+                        busy_o = yield cu.busy_o
+                        print ("busy", busy_o)
+                        if not busy_o:
+                            break
+                        yield
+
                     yield from self.iodef.check_cu_outputs(res, pdecode2,
                                                             sim, code)
 
diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index dccdaa8c..692fc668 100644
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -76,7 +76,7 @@ class LDSTTestCase(FHDLTestCase):
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)
 
-    def tst_2_load_store(self):
+    def test_2_load_store(self):
         lst = ["stw 2, 0(1)",
                "lwz 3, 0(1)"]
         initial_regs = [0] * 32
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 9d00476d..fbe792b5 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -159,7 +159,7 @@ class DecoderTestCase(FHDLTestCase):
         print("qemu pc", hex(qpc))
         print("qemu cr", hex(qcr))
         print("qemu xer", bin(qxer))
-        print("sim pc", sim.pc.CIA.value)
+        print("sim pc", hex(sim.pc.CIA.value))
         print("sim cr", hex(sim_cr))
         print("sim xer", hex(sim_xer))
         self.assertEqual(qcr, sim_cr)