From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 04:16:59 +0000 (+0000)
Subject: fix niggles in offset calculation for LD with elwidth
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f28fad9fe4dde9ae710719cdea3d30c9b18b9a5a;p=riscv-isa-sim.git

fix niggles in offset calculation for LD with elwidth
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 3d53d78..55c225b 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -214,6 +214,14 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rvc_rs1s()),
                 insn._rvc_rs1s().reg);
+#endif
+#ifdef INSN_LD
+    fprintf(stderr, "pre %s %x vloop %d %d %d" \
+                      "vlen %d stop %d pred %lx rdv %lx rvc_rs1 %ld\n",
+                xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
+                vlen, insn.stop_vloop(),
+                dest_pred & (1<<voffs), READ_REG(insn._rs1()),
+                insn._rs1().reg);
 #endif
       #include INCLUDEFILE
 #ifdef DEST_PREDINT
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 7f6aded..aa1d9af 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -168,9 +168,9 @@ reg_t sv_proc_t::READ_REG(reg_spec_t const& spec,
     {
         // offset data to load by the number of BYTES not bits
         ndata = data + (bitwidth * shift / 8);
-        fprintf(stderr, "readreg ADDRmode %ld bitwidth %d offs %d " \
+        fprintf(stderr, "readreg ADDRmode %ld %ld bitwidth %d offs %d " \
                         "shift %d %lx->%lx\n",
-                        spec.reg, bitwidth, offs, shift, data, ndata);
+                        spec.reg, reg, bitwidth, offs, shift, data, ndata);
     }
     else
     {
@@ -950,34 +950,41 @@ sv_reg_t sv_proc_t::mmu_load(reg_spec_t const& spec, sv_reg_t const& offs,
     // addr_mode doesn't truncate the register to elwidth-specified
     // bitsize, it adds a modulo-offset based on the current VL loop index
     reg_t reg = READ_REG(spec, true, width);
-    sv_reg_t addr = rv_add(reg, offs);
+    sv_reg_t addr = sv_reg_t((uint64_t)reg + (int64_t)offs);
+    sv_reg_t v(0);
 
     // now that the address has been moved on by the modulo-offset,
     // get only an elwidth-sized element (if not "default")
     width = get_bitwidth(_insn->reg_elwidth(spec.reg, true), width);
+    fprintf(stderr, "mmu_load wid %ld addr %lx offs %lx\n",
+                    width, (uint64_t)reg, (int64_t)offs);
     switch (width)
     {
         case 8:
-            if (ext) return p->get_mmu()->load_uint8(addr);
-            else     return p->get_mmu()->load_int8(addr);
+            if (ext) v = p->get_mmu()->load_uint8(addr);
+            else     v = p->get_mmu()->load_int8(addr);
+            break;
         case 16:
-            if (ext) return p->get_mmu()->load_uint16(addr);
-            else     return p->get_mmu()->load_int16(addr);
+            if (ext) v = p->get_mmu()->load_uint16(addr);
+            else     v = p->get_mmu()->load_int16(addr);
             break;
         case 32:
-            if (ext) return p->get_mmu()->load_uint32(addr);
-            else     return p->get_mmu()->load_int32(addr);
+            if (ext) v = p->get_mmu()->load_uint32(addr);
+            else     v = p->get_mmu()->load_int32(addr);
             break;
         case 64:
-            if (ext) return p->get_mmu()->load_uint64(addr);
-            else     return p->get_mmu()->load_int64(addr);
+            if (ext) v = p->get_mmu()->load_uint64(addr);
+            else     v = p->get_mmu()->load_int64(addr);
             break;
     }
-    return 0; // XXX should never get here!
+    fprintf(stderr, "mmu_load wid %ld addr %lx offs %lx loaded %lx\n",
+                    width, (uint64_t)reg, (int64_t)offs, (uint64_t)v);
+    return v;
 }
 
 sv_reg_t sv_proc_t::adjust_load(sv_reg_t const& v, size_t width, bool ext)
 {
+    fprintf(stderr, "mmu_adjust \n");
     return v;
 }