From: Samuel Pitoiset Date: Thu, 5 Jul 2018 10:54:18 +0000 (+0200) Subject: radv: only flush CB meta in pipeline image barriers when needed X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2a310849ee2ae2ad46b6fca9723bf5f9e425c52;p=mesa.git radv: only flush CB meta in pipeline image barriers when needed If the given image doesn't enable CMASK, FMASK or DCC that's useless to flush CB metadata. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index da6748edff2..b7519dce49c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1978,8 +1978,10 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; break; case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT: - flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | - RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; + if (!image || (image && radv_image_has_CB_metadata(image))) { + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; + } break; case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT: flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 0a34d79a206..4e4b3a6037a 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1486,6 +1486,17 @@ radv_dcc_enabled(const struct radv_image *image, unsigned level) level < image->surface.num_dcc_levels; } +/** + * Return whether the image has CB metadata. + */ +static inline bool +radv_image_has_CB_metadata(const struct radv_image *image) +{ + return radv_image_has_cmask(image) || + radv_image_has_fmask(image) || + radv_image_has_dcc(image); +} + /** * Return whether the image has HTILE metadata for depth surfaces. */