From: Richard Sandiford <richard.sandiford@arm.com>
Date: Sun, 5 Jul 2015 07:59:14 +0000 (+0000)
Subject: target-insns.def (clear_cache): New targetm instruction pattern.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2cf13bd7c00ec7d12e7bddfefeb5eea84a14f74;p=gcc.git

target-insns.def (clear_cache): New targetm instruction pattern.

gcc/
	* target-insns.def (clear_cache): New targetm instruction pattern.
	* builtins.c (expand_builtin___clear_cache): Use it instead of
	HAVE_*/gen_* interface.

From-SVN: r225430
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eca124b6b31..a0fa9747d68 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-07-05  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* target-insns.def (clear_cache): New targetm instruction pattern.
+	* builtins.c (expand_builtin___clear_cache): Use it instead of
+	HAVE_*/gen_* interface.
+
 2015-07-05  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* target-insns.def (allocate_stack, check_stack, probe_stack)
diff --git a/gcc/builtins.c b/gcc/builtins.c
index 3110d0ae30f..f5923b12016 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -4807,20 +4807,22 @@ expand_builtin_copysign (tree exp, rtx target, rtx subtarget)
 /* Expand a call to __builtin___clear_cache.  */
 
 static rtx
-expand_builtin___clear_cache (tree exp ATTRIBUTE_UNUSED)
+expand_builtin___clear_cache (tree exp)
 {
-#ifndef HAVE_clear_cache
+  if (!targetm.code_for_clear_cache)
+    {
 #ifdef CLEAR_INSN_CACHE
-  /* There is no "clear_cache" insn, and __clear_cache() in libgcc
-     does something.  Just do the default expansion to a call to
-     __clear_cache().  */
-  return NULL_RTX;
+      /* There is no "clear_cache" insn, and __clear_cache() in libgcc
+	 does something.  Just do the default expansion to a call to
+	 __clear_cache().  */
+      return NULL_RTX;
 #else
-  /* There is no "clear_cache" insn, and __clear_cache() in libgcc
-     does nothing.  There is no need to call it.  Do nothing.  */
-  return const0_rtx;
+      /* There is no "clear_cache" insn, and __clear_cache() in libgcc
+	 does nothing.  There is no need to call it.  Do nothing.  */
+      return const0_rtx;
 #endif /* CLEAR_INSN_CACHE */
-#else
+    }
+
   /* We have a "clear_cache" insn, and it will handle everything.  */
   tree begin, end;
   rtx begin_rtx, end_rtx;
@@ -4834,7 +4836,7 @@ expand_builtin___clear_cache (tree exp ATTRIBUTE_UNUSED)
       return const0_rtx;
     }
 
-  if (HAVE_clear_cache)
+  if (targetm.have_clear_cache ())
     {
       struct expand_operand ops[2];
 
@@ -4846,11 +4848,10 @@ expand_builtin___clear_cache (tree exp ATTRIBUTE_UNUSED)
 
       create_address_operand (&ops[0], begin_rtx);
       create_address_operand (&ops[1], end_rtx);
-      if (maybe_expand_insn (CODE_FOR_clear_cache, 2, ops))
+      if (maybe_expand_insn (targetm.code_for_clear_cache, 2, ops))
 	return const0_rtx;
     }
   return const0_rtx;
-#endif /* HAVE_clear_cache */
 }
 
 /* Given a trampoline address, make sure it satisfies TRAMPOLINE_ALIGNMENT.  */
diff --git a/gcc/target-insns.def b/gcc/target-insns.def
index 28d3151b3fc..2a9b23bafe6 100644
--- a/gcc/target-insns.def
+++ b/gcc/target-insns.def
@@ -37,6 +37,7 @@ DEF_TARGET_INSN (builtin_setjmp_setup, (rtx x0))
 DEF_TARGET_INSN (canonicalize_funcptr_for_compare, (rtx x0, rtx x1))
 DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4))
 DEF_TARGET_INSN (check_stack, (rtx x0))
+DEF_TARGET_INSN (clear_cache, (rtx x0, rtx x1))
 DEF_TARGET_INSN (epilogue, (void))
 DEF_TARGET_INSN (exception_receiver, (void))
 DEF_TARGET_INSN (jump, (rtx x0))