From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 18 Sep 2019 08:45:38 +0000 (+0200)
Subject: soc/cores/timer: fix typo (thanks xobs)
X-Git-Tag: 24jan2021_ls180~1009
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2e84a5800223d974b06cdb6dd6e42492fcbb875;p=litex.git

soc/cores/timer: fix typo (thanks xobs)
---

diff --git a/litex/soc/cores/timer.py b/litex/soc/cores/timer.py
index 7055254c..e13a76fd 100644
--- a/litex/soc/cores/timer.py
+++ b/litex/soc/cores/timer.py
@@ -19,7 +19,7 @@ class Timer(Module, AutoCSR):
         self._reload = CSRStorage(width, description=
             """Reload value when timer reaches 0.
             This register is used to create a Periodic timer and specify the timer's period in clock
-            cycles. For a One-Shot timer, this register need to be set to 0.""")
+            cycles. For a One-Shot timer, this register needs to be set to 0.""")
         self._en = CSRStorage(1, description=
             """Enable. Write 1 to enable/start the timer, 0 to disable the timer""")
         self._update_value = CSRStorage(1, description=