From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 28 Jul 2015 14:36:42 +0000 (+0800)
Subject: soc: increase default BIOS size
X-Git-Tag: 24jan2021_ls180~2176
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f2eff4d10ed487b05e76125be7c668753c319a83;p=litex.git

soc: increase default BIOS size
---

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index ef7c4545..0280cba7 100644
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -146,7 +146,7 @@ class SoC(Module):
         if size is not None:
             self.add_memory_region(name, address, size)
 
-    def register_rom(self, interface, rom_size=0xa000):
+    def register_rom(self, interface, rom_size=0x10000):
         self.add_wb_slave(mem_decoder(self.mem_map["rom"]), interface)
         self.add_memory_region("rom", self.cpu_reset_address, rom_size)