From: lkcl <lkcl@web>
Date: Mon, 5 Sep 2022 16:24:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~672
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f309cbd4f156b857d8e4721bfff577dcd6de28f5;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index be9a5069d..1d2fa4ae5 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -28,8 +28,8 @@ Modes apply to Arithmetic and Logical SVP64 operations:
   *VL is altered as a result*.
 * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping for both INT
 and FP.
-* **reduce mode**. if used correftly, a mapreduce (or a prefix sum)
-  is performed.    see [[svp64/appendix]]:
+* **reduce mode**. if used correctly, a mapreduce (or a prefix sum)
+  is performed.    see [[svp64/appendix]].
   note that there are comprehensive caveats when using this mode.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch conditional testing) and if the test fails it
 is as if the