From: lkcl <lkcl@web>
Date: Mon, 10 Apr 2023 22:02:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~18
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f310430d5ca4b48907db352bfe8fff7ac2b30929;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 586c96e9e..4a136b93d 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -141,7 +141,7 @@ it is also possible to perform prefix-sum (Fibonacci Series) in certain
 circumstances. Details are in the [[svp64/appendix]]
 
 Reduce Mode should not be confused with Parallel Reduction [[sv/remap]].
-As explained in the [[sv/appendix]] Reduce Mode switches off the check
+As explained in the [[sv/svp64/appendix]] Reduce Mode switches off the check
 which would normally stop looping if the result register is scalar.
 Thus, the result scalar register, if also used as a source scalar,
 may be used to perform sequential accumulation. This *deliberately*