From: Luke Kenneth Casson Leighton Date: Wed, 13 May 2020 18:18:06 +0000 (+0100) Subject: Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f314a88904a5f219e4e7d555e6513799032e6ddb;p=libre-riscv-dev.git Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog --- diff --git a/9f/0f352016c518a90a526662879d2c7ed1c236bb b/9f/0f352016c518a90a526662879d2c7ed1c236bb new file mode 100644 index 0000000..9149f6d --- /dev/null +++ b/9f/0f352016c518a90a526662879d2c7ed1c236bb @@ -0,0 +1,95 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 13 May 2020 19:18:31 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jYvxe-0007H0-JB; Wed, 13 May 2020 19:18:30 +0100 +Received: from lkcl.net ([217.147.94.29]) + by libre-soc.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jYvxd-0007Gk-6P + for libre-riscv-dev@lists.libre-riscv.org; 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