From: Gavin Romig-Koch Date: Thu, 19 Feb 1998 15:24:10 +0000 (+0000) Subject: * interp.c (load_memory): Add missing "break"'s. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f319bab25103e2beb3d90ce94907eb0b0a5dc96d;p=binutils-gdb.git * interp.c (load_memory): Add missing "break"'s. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 9c9d2b90d60..4646aa44baf 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,16 @@ +Thu Feb 19 10:21:21 1998 Gavin Koch + + * interp.c (load_memory): Add missing "break"'s. + +Tue Feb 17 12:45:35 1998 Andrew Cagney + + * interp.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Tue Feb 10 11:57:40 1998 Ian Carmichael + + * interp.c: Added hardware init hook, fixed warnings. + Sat Feb 7 17:16:20 1998 Andrew Cagney * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. diff --git a/sim/mips/interp.c b/sim/mips/interp.c index c591abf3b5d..be3d71d306d 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -586,11 +586,12 @@ sim_read (sd,addr,buffer,size) return(index); } -void -sim_store_register (sd,rn,memory) +int +sim_store_register (sd,rn,memory,length) SIM_DESC sd; int rn; unsigned char *memory; + int length; { sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ /* NOTE: gdb (the client) stores registers in target byte order @@ -645,14 +646,15 @@ sim_store_register (sd,rn,memory) else cpu->registers[rn] = T2H_8 (*(unsigned64*)memory); - return; + return -1; } -void -sim_fetch_register (sd,rn,memory) +int +sim_fetch_register (sd,rn,memory,length) SIM_DESC sd; int rn; unsigned char *memory; + int length; { sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ /* NOTE: gdb (the client) stores registers in target byte order @@ -703,7 +705,7 @@ sim_fetch_register (sd,rn,memory) else /* 64bit register */ *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn])); - return; + return -1; } @@ -1478,12 +1480,15 @@ load_memory (SIM_DESC sd, case AccessLength_SEPTIBYTE : value = sim_core_read_misaligned_7 (cpu, NULL_CIA, sim_core_read_map, pAddr); + break; case AccessLength_SEXTIBYTE : value = sim_core_read_misaligned_6 (cpu, NULL_CIA, sim_core_read_map, pAddr); + break; case AccessLength_QUINTIBYTE : value = sim_core_read_misaligned_5 (cpu, NULL_CIA, sim_core_read_map, pAddr); + break; case AccessLength_WORD : value = sim_core_read_aligned_4 (cpu, NULL_CIA, sim_core_read_map, pAddr); @@ -1491,6 +1496,7 @@ load_memory (SIM_DESC sd, case AccessLength_TRIPLEBYTE : value = sim_core_read_misaligned_3 (cpu, NULL_CIA, sim_core_read_map, pAddr); + break; case AccessLength_HALFWORD : value = sim_core_read_aligned_2 (cpu, NULL_CIA, sim_core_read_map, pAddr);