From: Richard Sandiford <richard.sandiford@linaro.org>
Date: Tue, 7 Nov 2017 16:08:47 +0000 (+0000)
Subject: [AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f32c3adb8d77c0ebee112ecf26ae249c8574970e;p=gcc.git

[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand

Some of the shift expanders accepted nonmemory_operands but were only
able to handle register_operands or CONST_INTs.  This is probably
academic without SVE, since we're not likely to see shifts by other
types of constant (const_wide_ints, consts, etc).  But for SVE,
it's possible for a vectorised shift induction to have a CONST_POLY_INT
shift amount.

This patch makes the expanders use aarch64_reg_or_imm instead.

2017-11-07  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
	(rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
	nonmmory_operand.

From-SVN: r254499
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f81b5d81567..db9ff08ddc8 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-11-07  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
+	(rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
+	nonmmory_operand.
+
 2017-11-07  Richard Biener  <rguenther@suse.de>
 
 	* match.pd: Fix build.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ce75cf4171d..423a3352aab 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3958,7 +3958,7 @@
 (define_expand "<optab><mode>3"
   [(set (match_operand:GPI 0 "register_operand")
 	(ASHIFT:GPI (match_operand:GPI 1 "register_operand")
-		    (match_operand:QI 2 "nonmemory_operand")))]
+		    (match_operand:QI 2 "aarch64_reg_or_imm")))]
   ""
   {
     if (CONST_INT_P (operands[2]))
@@ -3994,7 +3994,7 @@
 (define_expand "rotr<mode>3"
   [(set (match_operand:GPI 0 "register_operand")
 	(rotatert:GPI (match_operand:GPI 1 "register_operand")
-		      (match_operand:QI 2 "nonmemory_operand")))]
+		      (match_operand:QI 2 "aarch64_reg_or_imm")))]
   ""
   {
     if (CONST_INT_P (operands[2]))
@@ -4014,7 +4014,7 @@
 (define_expand "rotl<mode>3"
   [(set (match_operand:GPI 0 "register_operand")
 	(rotatert:GPI (match_operand:GPI 1 "register_operand")
-		      (match_operand:QI 2 "nonmemory_operand")))]
+		      (match_operand:QI 2 "aarch64_reg_or_imm")))]
   ""
   {
     /* (SZ - cnt) % SZ == -cnt % SZ */