From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 17 Aug 2014 00:16:56 +0000 (+0200)
Subject: Improved sig.remove2() performance
X-Git-Tag: yosys-0.4~238
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3326a642178b66ba98b6371245077ff93ffe215;p=yosys.git

Improved sig.remove2() performance
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 60c514d19..e4bf4f9f3 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2182,14 +2182,23 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
 
 	std::vector<RTLIL::SigBit> new_bits, new_other_bits;
 
+	new_bits.resize(SIZE(bits_));
+	if (other != NULL)
+		new_other_bits.resize(SIZE(bits_));
+
+	int k = 0;
 	for (int i = 0; i < SIZE(bits_); i++) {
 		if (bits_[i].wire != NULL && pattern.count(bits_[i]))
 			continue;
 		if (other != NULL)
-			new_other_bits.push_back(other->bits_[i]);
-		new_bits.push_back(bits_[i]);
+			new_other_bits[k] = other->bits_[i];
+		new_bits[k++] = bits_[i];
 	}
 
+	new_bits.resize(k);
+	if (other != NULL)
+		new_other_bits.resize(k);
+
 	bits_.swap(new_bits);
 	width_ = SIZE(bits_);