From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 12:14:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2378
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3390792b874b993fd3c1d75aef6fa98d6ddab8d;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index c8101fdef..75a532aa8 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -534,5 +534,10 @@ and apply deterministic nested loop schedules to more than just registers
 
 **OpenCAPI and Extra-V**
 
+OpenCAPI is a deterministic high-performance, high-bandwidth, low-latency
+cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputing-class POWER9 and POWER10 processors. POWER10 *only*
+has OpenCAPI interfaces, and requires an OpenCAPI-to-DDR4/5 Bridge PHY
+to connect to standard DIMMs.
+
 **Snitch**