From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 3 Sep 2020 07:45:23 +0000 (+0100)
Subject: testing microwatt 3.bin (2.bin ok)
X-Git-Tag: semi_working_ecp5~209
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f33a505f7bb73b1ae8682716bf2e5dd63c601b27;p=soc.git

testing microwatt 3.bin (2.bin ok)
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index afe4140f..ce746dd4 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -49,7 +49,7 @@ class LibreSoCSim(SoCSDRAM):
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/1.bin"
+                    "tests/3.bin"
         #ram_fname = "/tmp/test.bin"
         #ram_fname = None
 
@@ -308,8 +308,8 @@ class LibreSoCSim(SoCSDRAM):
         )
 
         if cpu == "libresoc":
-            self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
-            #self.comb += active_dbg_cr.eq(1)
+            #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
+            self.comb += active_dbg_cr.eq(0)
 
             # get the CR
             self.sync += If(active_dbg_cr & (dmicount == 16),