From: Tobias Platen <tplaten@posteo.de>
Date: Tue, 12 Apr 2022 18:47:34 +0000 (+0200)
Subject: cleanup Makefile
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f33e4fe47d0eacf7583d87f38ab596ae4c0c6e13;p=microwatt.git

cleanup Makefile
---

diff --git a/Makefile b/Makefile
index b061ddb..b99adf0 100644
--- a/Makefile
+++ b/Makefile
@@ -146,7 +146,7 @@ $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_f
 	$(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(soc_dram_files) $(soc_dram_sim_files) $(flash_model_files) $@.vhdl -e $@
 endif
 
-# Hello world
+# Hello world - working using libre-soc core
 MEMORY_SIZE ?=8192
 RAM_INIT_FILE ?=hello_world/hello_world.hex
 
@@ -154,6 +154,14 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex
 #MEMORY_SIZE=393216
 #RAM_INIT_FILE=micropython/firmware.hex
 
+# Linux
+#MEMORY_SIZE=536870912
+#RAM_INIT_FILE=dtbImage.microwatt.hex
+#SIM_MAIN_BRAM=false
+#SIM_BRAM_CHAINBOOT=6291456 # 0x600000
+#SIM_MAIN_BRAM=false
+
+
 FPGA_TARGET ?= ORANGE-CRAB-0.21
 
 # FIXME: icache RAMs aren't being inferrenced as block RAMs on ECP5
@@ -224,16 +232,11 @@ soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
 soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v
 endif
 
- GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
+GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
 	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
-	$(LITEDRAM_GHDL_ARG) -gEXTERNAL_CORE=true #-gEXTERNAL_CORE=$(EXTERNAL_CORE)
+	$(LITEDRAM_GHDL_ARG) -gEXTERNAL_CORE=$(EXTERNAL_CORE) \
+	-gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) 
 	
-#GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-#	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
-#	-gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) ...
-	
-
-
 ifeq ($(FPGA_TARGET), verilator)
 RESET_LOW=true
 CLK_INPUT=50000000
@@ -251,8 +254,6 @@ _soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
 	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
 	spi_rxtx.vhdl spi_flash_ctrl.vhdl plru_dummy.vhdl
 
-
-#--
 # use an alternative core (in verilog)
 EXTERNAL_CORE=true
 ifeq ($(EXTERNAL_CORE),false)
@@ -263,14 +264,12 @@ ifeq ($(EXTERNAL_CORE),false)
 
 	synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 else
-#incomplete: does not build yet
     util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
                 core_dummy.vhdl helpers.vhdl gpio.vhdl cache_ram.vhdl 
     fpga_files = $(_fpga_files) $(_soc_files)
     synth_files = $(util_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
     soc_extra_v = external_core_top.v
 endif
-#--
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE) $(soc_extra_v)
 	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
@@ -285,10 +284,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 microwatt.v.old: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 	
-	
-#MEMORY_SIZE=16777216 # 268435456
-#RAM_INIT_FILE=dtbImage.microwatt.hex
-SIM_MAIN_BRAM=true
+
 	
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 # --top-module toplevel