From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 02:01:13 +0000 (-0700)
Subject: Use \$currQ
X-Git-Tag: working-ls180~881^2^2~271
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3511e4f9358b0eb053893877ab615b66325da39;p=yosys.git

Use \$currQ
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index d0087501d..96cbb1e04 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -66,8 +66,13 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
-  \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  generate
+    if (IS_PRE_INVERTED)
+      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
+    else
+      \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));
+  endgenerate
 endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
@@ -99,7 +104,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   generate
     if (IS_PRE_INVERTED)
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
@@ -117,7 +122,7 @@ module FDPE_1 (output reg Q, input C, CE, D, CLR);
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
   );
-  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
 endmodule