From: Marcus Comstedt Date: Tue, 5 Jan 2021 21:50:39 +0000 (+0100) Subject: RISC-V: Fix riscv gas/ld testsuites failures for big endian. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f36ce378b46fd6a1451553e886502d39bec6edea;p=binutils-gdb.git RISC-V: Fix riscv gas/ld testsuites failures for big endian. Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct linker script rather than set elf[32|64]lriscv directly. gas/ * testsuite/gas/riscv/li32.d: Accept bigriscv in addition to littleriscv. * testsuite/gas/riscv/li64.d: Likewise. * testsuite/gas/riscv/lla32.d: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. * testsuite/ld-riscv-elf/c-lui.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition to littleriscv. * testsuite/ld-riscv-elf/weakref64.d: Likewise. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 57bc038a563..4c500edaa87 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,18 @@ +2021-01-06 Marcus Comstedt + + * testsuite/gas/riscv/li32.d: Accept bigriscv in addition + to littleriscv. + * testsuite/gas/riscv/li64.d: Likewise. + * testsuite/gas/riscv/lla32.d: Likewise. + * testsuite/gas/riscv/lla64.d: Likewise. + * testsuite/gas/riscv/march-ok-g2.d: Likewise. + * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. + * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. + * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. + * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. + * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. + * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. + 2021-01-06 Marcus Comstedt * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and diff --git a/gas/testsuite/gas/riscv/li32.d b/gas/testsuite/gas/riscv/li32.d index ff0827dde99..947ea4f754a 100644 --- a/gas/testsuite/gas/riscv/li32.d +++ b/gas/testsuite/gas/riscv/li32.d @@ -1,7 +1,7 @@ #as: -march=rv32ic -mabi=ilp32 #objdump: -dr -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv Disassembly of section .text: diff --git a/gas/testsuite/gas/riscv/li64.d b/gas/testsuite/gas/riscv/li64.d index 54213031cc5..498b2e513d9 100644 --- a/gas/testsuite/gas/riscv/li64.d +++ b/gas/testsuite/gas/riscv/li64.d @@ -1,7 +1,7 @@ #as: -march=rv64ic -mabi=lp64 #objdump: -dr -.*: file format elf64-littleriscv +.*: file format elf64-(little|big)riscv Disassembly of section .text: diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d index ab766b4e3b6..9d875629064 100644 --- a/gas/testsuite/gas/riscv/lla32.d +++ b/gas/testsuite/gas/riscv/lla32.d @@ -1,7 +1,7 @@ #as: -march=rv32i -mabi=ilp32 #objdump: -dr -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv Disassembly of section .text: diff --git a/gas/testsuite/gas/riscv/lla64.d b/gas/testsuite/gas/riscv/lla64.d index 7848eecdfb0..c3b95818625 100644 --- a/gas/testsuite/gas/riscv/lla64.d +++ b/gas/testsuite/gas/riscv/lla64.d @@ -1,7 +1,7 @@ #as: -march=rv64i -mabi=lp64 #objdump: -dr -.*: file format elf64-littleriscv +.*: file format elf64-(little|big)riscv Disassembly of section .text: diff --git a/gas/testsuite/gas/riscv/march-ok-g2.d b/gas/testsuite/gas/riscv/march-ok-g2.d index 38541ad6a6c..7c92bc8bcb1 100644 --- a/gas/testsuite/gas/riscv/march-ok-g2.d +++ b/gas/testsuite/gas/riscv/march-ok-g2.d @@ -2,4 +2,4 @@ #objdump: -dr #source: empty.s -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv diff --git a/gas/testsuite/gas/riscv/march-ok-g2_p1.d b/gas/testsuite/gas/riscv/march-ok-g2_p1.d index cd9e127e669..da2247c9d9e 100644 --- a/gas/testsuite/gas/riscv/march-ok-g2_p1.d +++ b/gas/testsuite/gas/riscv/march-ok-g2_p1.d @@ -2,4 +2,4 @@ #objdump: -dr #source: empty.s -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv diff --git a/gas/testsuite/gas/riscv/march-ok-g2p0.d b/gas/testsuite/gas/riscv/march-ok-g2p0.d index b439314ccf5..a11d55e4990 100644 --- a/gas/testsuite/gas/riscv/march-ok-g2p0.d +++ b/gas/testsuite/gas/riscv/march-ok-g2p0.d @@ -2,4 +2,4 @@ #objdump: -dr #source: empty.s -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0.d b/gas/testsuite/gas/riscv/march-ok-i2p0.d index eb8309c7e28..e413e09f88d 100644 --- a/gas/testsuite/gas/riscv/march-ok-i2p0.d +++ b/gas/testsuite/gas/riscv/march-ok-i2p0.d @@ -2,4 +2,4 @@ #objdump: -dr #source: empty.s -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv diff --git a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d index 6658417b0fb..11960ba5bfa 100644 --- a/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d +++ b/gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d @@ -2,4 +2,4 @@ #objdump: -dr #source: empty.s -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv diff --git a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d index bdca7fb18db..8e2110cef4e 100644 --- a/gas/testsuite/gas/riscv/march-ok-nse-with-version.d +++ b/gas/testsuite/gas/riscv/march-ok-nse-with-version.d @@ -2,4 +2,4 @@ #objdump: -dr #source: empty.s -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv diff --git a/gas/testsuite/gas/riscv/march-ok-two-nse.d b/gas/testsuite/gas/riscv/march-ok-two-nse.d index e78cf9dd09b..8cdf316f048 100644 --- a/gas/testsuite/gas/riscv/march-ok-two-nse.d +++ b/gas/testsuite/gas/riscv/march-ok-two-nse.d @@ -2,4 +2,4 @@ #objdump: -dr #source: empty.s -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv diff --git a/ld/ChangeLog b/ld/ChangeLog index 2e51333bb1b..23a07195318 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,22 @@ +2021-01-06 Marcus Comstedt + + * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added + riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. + * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call + riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. + * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. + * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. + * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. + * testsuite/ld-riscv-elf/c-lui.d: Likewise. + * testsuite/ld-riscv-elf/call-relax.d: Likewise. + * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. + * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. + * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition + to littleriscv. + * testsuite/ld-riscv-elf/weakref64.d: Likewise. + 2021-01-06 Marcus Comstedt * configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*, diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d index 5baaba4c16f..c148cdbc4f4 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d @@ -1,7 +1,7 @@ #source: attr-merge-arch-01a.s #source: attr-merge-arch-01b.s #as: -#ld: -r -melf32lriscv +#ld: -r -m[riscv_choose_ilp32_emul] #readelf: -A Attribute Section: riscv diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d index a7d79a1ea2b..bc0e0fd1384 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d @@ -1,7 +1,7 @@ #source: attr-merge-arch-02a.s #source: attr-merge-arch-02b.s #as: -#ld: -r -melf32lriscv +#ld: -r -m[riscv_choose_ilp32_emul] #readelf: -A Attribute Section: riscv diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d index d46dee808de..374a043c69e 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d @@ -1,7 +1,7 @@ #source: attr-merge-arch-03a.s #source: attr-merge-arch-03b.s #as: -#ld: -r -melf32lriscv +#ld: -r -m[riscv_choose_ilp32_emul] #readelf: -A Attribute Section: riscv diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d index 4b312388f72..669a1392067 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d @@ -1,7 +1,7 @@ #source: attr-merge-arch-failed-01a.s #source: attr-merge-arch-failed-01b.s #as: -march-attr -#ld: -r -melf32lriscv +#ld: -r -m[riscv_choose_ilp32_emul] #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0 #readelf: -A diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d index 880ee154737..3f4935df54c 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d @@ -3,7 +3,7 @@ #source: attr-merge-arch-failed-02c.s #source: attr-merge-arch-failed-02d.s #as: -march-attr -#ld: -r -melf32lriscv +#ld: -r -m[riscv_choose_ilp32_emul] #warning: .*mis-matched ISA version 3.0 for 'i' extension, the output version is 2.0 #warning: .*mis-matched ISA version 3.0 for 'm' extension, the output version is 2.0 #warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0 diff --git a/ld/testsuite/ld-riscv-elf/c-lui-2.d b/ld/testsuite/ld-riscv-elf/c-lui-2.d index 622c0f7a31d..d363da10c33 100644 --- a/ld/testsuite/ld-riscv-elf/c-lui-2.d +++ b/ld/testsuite/ld-riscv-elf/c-lui-2.d @@ -1,7 +1,7 @@ #name: c.lui to c.li relaxation #source: c-lui-2.s #as: -march=rv32ic -#ld: -melf32lriscv -Tc-lui-2.ld +#ld: -m[riscv_choose_ilp32_emul] -Tc-lui-2.ld #objdump: -d -M no-aliases,numeric .*: file format .* diff --git a/ld/testsuite/ld-riscv-elf/c-lui.d b/ld/testsuite/ld-riscv-elf/c-lui.d index 382eca88dc2..f1cf0b42c30 100644 --- a/ld/testsuite/ld-riscv-elf/c-lui.d +++ b/ld/testsuite/ld-riscv-elf/c-lui.d @@ -1,7 +1,7 @@ #name: lui to c.lui relaxation #source: c-lui.s #as: -march=rv32ic -#ld: -melf32lriscv +#ld: -m[riscv_choose_ilp32_emul] #objdump: -d -M no-aliases,numeric .*: file format .* diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d index 597ff675353..c6022bec262 100644 --- a/ld/testsuite/ld-riscv-elf/call-relax.d +++ b/ld/testsuite/ld-riscv-elf/call-relax.d @@ -4,6 +4,6 @@ #source: call-relax-2.s #source: call-relax-3.s #as: -march=rv32ic -mno-arch-attr -#ld: -melf32lriscv +#ld: -m[riscv_choose_ilp32_emul] #objdump: -d #pass diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp index eb3df7673ac..7081af1e8e3 100644 --- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp +++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp @@ -19,6 +19,24 @@ # MA 02110-1301, USA. # +proc riscv_choose_ilp32_emul {} { + if { [istarget "riscvbe-*"] \ + || [istarget "riscv32be-*"] \ + || [istarget "riscv64be-*"] } { + return "elf32briscv" + } + return "elf32lriscv" +} + +proc riscv_choose_lp64_emul {} { + if { [istarget "riscvbe-*"] \ + || [istarget "riscv32be-*"] \ + || [istarget "riscv64be-*"] } { + return "elf64briscv" + } + return "elf64lriscv" +} + # target: rv32 or rv64. # output: Which output you want? (exe, pie, .so) proc run_dump_test_ifunc { name target output} { @@ -42,11 +60,11 @@ proc run_dump_test_ifunc { name target output} { switch -- $target { rv32 { set asflags "$asflags -march=rv32i -mabi=ilp32" - set ldflags "$ldflags -melf32lriscv" + set ldflags "$ldflags -m[riscv_choose_ilp32_emul]" } rv64 { set asflags "$asflags -march=rv64i -mabi=lp64 -defsym __64_bit__=1" - set ldflags "$ldflags -melf64lriscv" + set ldflags "$ldflags -m[riscv_choose_lp64_emul]" } } @@ -89,21 +107,20 @@ if [istarget "riscv*-*-*"] { run_dump_test "attr-merge-priv-spec-failed-04" run_dump_test "attr-merge-priv-spec-failed-05" run_dump_test "attr-merge-priv-spec-failed-06" - run_ld_link_tests { - { "Weak reference 32" "-T weakref.ld -melf32lriscv" "" - "-march=rv32i -mabi=ilp32" {weakref32.s} - {{objdump -d weakref32.d}} "weakref32"} - { "Weak reference 64" "-T weakref.ld -melf64lriscv" "" - "-march=rv64i -mabi=lp64" {weakref64.s} - {{objdump -d weakref64.d}} "weakref64"} - } + run_ld_link_tests [list \ + [list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \ + "-march=rv32i -mabi=ilp32" {weakref32.s} \ + {{objdump -d weakref32.d}} "weakref32"] \ + [list "Weak reference 64" "-T weakref.ld -m[riscv_choose_lp64_emul]" "" \ + "-march=rv64i -mabi=lp64" {weakref64.s} \ + {{objdump -d weakref64.d}} "weakref64"]] # The following tests require shared library support. if ![check_shared_lib_support] { return } - set abis { rv32gc ilp32 elf32lriscv rv64gc lp64 elf64lriscv } + set abis [list rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul]] foreach { arch abi emul } $abis { # This checks whether our linker scripts handle __global_pointer$ # correctly. It should be defined in executables and PIE, but not diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d index 039de102c3a..895c6cc5814 100644 --- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d +++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d @@ -1,5 +1,5 @@ #name: %pcrel_lo overflow with an addend #source: pcrel-lo-addend-2.s #as: -march=rv32ic -#ld: -melf32lriscv --no-relax +#ld: -m[riscv_choose_ilp32_emul] --no-relax #error: .*dangerous relocation: %pcrel_lo overflow with an addend diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d index ad658be844e..92d41528a4a 100644 --- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d +++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d @@ -1,5 +1,5 @@ #name: %pcrel_lo section symbol with an addend #source: pcrel-lo-addend.s #as: -march=rv32ic -#ld: -melf32lriscv +#ld: -m[riscv_choose_ilp32_emul] #error: .*dangerous relocation: %pcrel_lo section symbol with an addend diff --git a/ld/testsuite/ld-riscv-elf/weakref32.d b/ld/testsuite/ld-riscv-elf/weakref32.d index eaeb6dae7e3..279481d2233 100644 --- a/ld/testsuite/ld-riscv-elf/weakref32.d +++ b/ld/testsuite/ld-riscv-elf/weakref32.d @@ -1,5 +1,5 @@ -.*: file format elf32-littleriscv +.*: file format elf32-(little|big)riscv Disassembly of section \.text: diff --git a/ld/testsuite/ld-riscv-elf/weakref64.d b/ld/testsuite/ld-riscv-elf/weakref64.d index cc718a91a31..c8f4c103398 100644 --- a/ld/testsuite/ld-riscv-elf/weakref64.d +++ b/ld/testsuite/ld-riscv-elf/weakref64.d @@ -1,5 +1,5 @@ -.*: file format elf64-littleriscv +.*: file format elf64-(little|big)riscv Disassembly of section \.text: