From: Iago Toral Quiroga <itoral@igalia.com>
Date: Thu, 17 Jul 2014 06:54:03 +0000 (+0200)
Subject: i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f373b7ed820024080838742f419bbca5fcbde2bf;p=mesa.git

i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.

We had GS_OPCODE_SET_DWORD_2_IMMED but this required its source argument to be
an immediate. In gen6 we need to set dword 2 of the URB write message header
from values stored in separate register, so we need something more flexible.
This change replaces GS_OPCODE_SET_DWORD_2_IMMED with GS_OPCODE_SET_DWORD_2.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 72a21e85d16..1e5a12b6a06 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -984,11 +984,9 @@ enum opcode {
    GS_OPCODE_SET_VERTEX_COUNT,
 
    /**
-    * Set DWORD 2 of dst to the immediate value in src.  Used by geometry
-    * shaders to initialize DWORD 2 of R0, which needs to be 0 in order for
-    * scratch reads and writes to operate correctly.
+    * Set DWORD 2 of dst to the value in src.
     */
-   GS_OPCODE_SET_DWORD_2_IMMED,
+   GS_OPCODE_SET_DWORD_2,
 
    /**
     * Prepare the dst register for storage in the "Channel Mask" fields of a
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index b2352468450..1c8bdb6ecd9 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -516,8 +516,8 @@ brw_instruction_name(enum opcode op)
       return "set_write_offset";
    case GS_OPCODE_SET_VERTEX_COUNT:
       return "set_vertex_count";
-   case GS_OPCODE_SET_DWORD_2_IMMED:
-      return "set_dword_2_immed";
+   case GS_OPCODE_SET_DWORD_2:
+      return "set_dword_2";
    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
       return "prepare_channel_masks";
    case GS_OPCODE_SET_CHANNEL_MASKS:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index cb863c80595..82e91a9a503 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -653,7 +653,7 @@ private:
                                      struct brw_reg src1);
    void generate_gs_set_vertex_count(struct brw_reg dst,
                                      struct brw_reg src);
-   void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
+   void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
    void generate_gs_prepare_channel_masks(struct brw_reg dst);
    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
    void generate_gs_get_instance_id(struct brw_reg dst);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index ebc54916c12..168536cd5e2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -574,16 +574,12 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
 }
 
 void
-vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst,
-                                              struct brw_reg src)
+vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
 {
-   assert(src.file == BRW_IMMEDIATE_VALUE);
-
    brw_push_insn_state(p);
    brw_set_default_access_mode(p, BRW_ALIGN_1);
    brw_set_default_mask_control(p, BRW_MASK_DISABLE);
-   brw_MOV(p, suboffset(vec1(dst), 2), src);
-   brw_set_default_access_mode(p, BRW_ALIGN_16);
+   brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
    brw_pop_insn_state(p);
 }
 
@@ -1355,8 +1351,8 @@ vec4_generator::generate_code(const cfg_t *cfg)
          generate_gs_ff_sync(inst, dst, src[0]);
          break;
 
-      case GS_OPCODE_SET_DWORD_2_IMMED:
-         generate_gs_set_dword_2_immed(dst, src[0]);
+      case GS_OPCODE_SET_DWORD_2:
+         generate_gs_set_dword_2(dst, src[0]);
          break;
 
       case GS_OPCODE_PREPARE_CHANNEL_MASKS:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index ad3204fcfe2..e0fd4206474 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -149,7 +149,7 @@ vec4_gs_visitor::emit_prolog()
     */
    this->current_annotation = "clear r0.2";
    dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
-   vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2_IMMED, r0, 0u);
+   vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, 0u);
    inst->force_writemask_all = true;
 
    /* Create a virtual register to hold the vertex count */