From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 17:18:01 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xc7mux
X-Git-Tag: working-ls180~1208^2~140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f374e0ab7e9a91fa86814b0f750660e92ed16ae6;p=yosys.git

Merge remote-tracking branch 'origin/master' into xc7mux
---

f374e0ab7e9a91fa86814b0f750660e92ed16ae6
diff --cc CHANGELOG
index 13cfb812b,4c38f6e6e..b9582fd63
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -17,13 -17,8 +17,14 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "rename -src"
      - Added "equiv_opt" pass
      - Added "read_aiger" frontend
 +    - Added "shregmap -tech xilinx"
++    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
+     - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 +    - Added "synth -abc9" (experimental)
-     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
  
  
  Yosys 0.7 .. Yosys 0.8