From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 20 Sep 2019 11:30:28 +0000 (+0200)
Subject: Merge pull request #1386 from YosysHQ/clifford/fix1360
X-Git-Tag: working-ls180~1051
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3781f98db227f160e08b2fc7cf8c61f663a56c9;p=yosys.git

Merge pull request #1386 from YosysHQ/clifford/fix1360

Fix handling of read_verilog config in AstModule::reprocess_module()
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f3781f98db227f160e08b2fc7cf8c61f663a56c9