From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 9 Mar 2022 08:48:29 +0000 (+0100)
Subject: Fixes and error check
X-Git-Tag: yosys-0.16~52^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f37ac5d934e76c12d7412451d45ded7a7df04b82;p=yosys.git

Fixes and error check
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index d7f4de507..79140e615 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1095,6 +1095,8 @@ struct SimWorker : SimShared
 	void run_cosim_aiger_witness(Module *topmod)
 	{
 		log_assert(top == nullptr);
+		if ((clock.size()+clockn.size())==0)
+			log_error("Clock signal must be specified.\n");
 		std::ifstream mf(map_filename);
 		std::string type, symbol;
 		int variable, index;
@@ -1213,6 +1215,8 @@ struct SimWorker : SimShared
 	void run_cosim_btor2_witness(Module *topmod)
 	{
 		log_assert(top == nullptr);
+		if ((clock.size()+clockn.size())==0)
+			log_error("Clock signal must be specified.\n");
 		std::ifstream f;
 		f.open(sim_filename.c_str());
 		if (f.fail() || GetSize(sim_filename) == 0)
@@ -1278,7 +1282,7 @@ struct SimWorker : SimShared
 					if ((int)parts[1].size() != w->width)
 						log_error("Size of wire %s is different than provided data.\n", log_signal(w));
 					
-					top->set_state(w, Const(parts[1]));					
+					top->set_state(w, Const::from_string(parts[1]));
 					break;
 			}
 		}