From: Florent Kermarrec Date: Thu, 20 Feb 2020 15:16:07 +0000 (+0100) Subject: integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with... X-Git-Tag: 24jan2021_ls180~648 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3829cf0819c2e5d0ebc6cffb9569f9f46191549;p=litex.git integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs. --- diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index bd896e0b..127aecec 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1001,4 +1001,5 @@ class LiteXSoC(SoC): self.add_config("L2_SIZE", l2_cache_size) # Wishbone Slave <--> LiteDRAM bridge -------------------------------------------------- - self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port) + self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(litedram_wb, port, + base_address = self.bus.regions["main_ram"].origin)