From: lkcl <lkcl@web>
Date: Thu, 5 May 2022 23:00:57 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2414
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f38871e6033dfae61e18da1278801d3269be1761;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index cd49217b5..97f68aff4 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -263,6 +263,10 @@ Once the basics of this concept have sunk in, early
 advancements quickly follow naturally from analysis
 of the problem-space:
 
+* Expanding the size of GPR, FPR and CR register files to
+  provide 128 entries in each. This is a bare minimum for GPUs
+  in order to keep processing workloads as close to a LOAD-COMPUTE-STORE
+  batching as possible.
 * Predication (an absolutely critical component for a Vector ISA),
   then the next logical advancement is to allow separate predication masks
   to be applied to *both* the source *and* the destination, independently.