From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Mar 2020 18:16:35 +0000 (+0000)
Subject: enable rvfi, fix imports
X-Git-Tag: div_pipeline~1706
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f390aac8bf2fc360589ec48e1d77c1afadadbf0d;p=soc.git

enable rvfi, fix imports
---

diff --git a/src/soc/minerva/core.py b/src/soc/minerva/core.py
index c73d5fd0..51e94e6d 100644
--- a/src/soc/minerva/core.py
+++ b/src/soc/minerva/core.py
@@ -14,7 +14,7 @@ from soc.minerva.units.decoder import InstructionDecoder
 from soc.minerva.units.divider import Divider, DummyDivider
 from soc.minerva.units.exception import ExceptionUnit
 from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit, PCSelector
-from soc.minerva.units.rvficon import RVFIController
+from soc.minerva.units.rvficon import RVFIController, rvfi_layout
 from soc.minerva.units.loadstore import (BareLoadStoreUnit, CachedLoadStoreUnit,
                                          DataSelector)
 from soc.minerva.units.logic import LogicUnit
diff --git a/src/soc/minerva/units/rvficon.py b/src/soc/minerva/units/rvficon.py
index 266fd12a..a167f496 100644
--- a/src/soc/minerva/units/rvficon.py
+++ b/src/soc/minerva/units/rvficon.py
@@ -1,7 +1,7 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import Elaboratable, Module, Signal, Record
+from nmigen import Elaboratable, Module, Signal, Record, Const
 from nmigen.hdl.rec import DIR_FANOUT
 
 from ..wishbone import wishbone_layout