From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Mon, 3 Feb 2020 11:03:57 +0000 (+0100)
Subject: tools/litex_sim: use l2_reverse flag
X-Git-Tag: 24jan2021_ls180~694^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3b068e2ee97ca004057a77be2b37ff751262276;p=litex.git

tools/litex_sim: use l2_reverse flag
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 097f8ed9..9993b1ff 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -168,6 +168,7 @@ class SimSoC(SoCSDRAM):
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
             ident               = "LiteX Simulation", ident_version=True,
             with_uart           = False,
+            l2_reverse          = False,
             **kwargs)
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))