From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 15:01:05 +0000 (+0200)
Subject: global: pep8 (E225)
X-Git-Tag: 24jan2021_ls180~2322
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3c010c1d5b737080a245929a870c3926402b4c8;p=litex.git

global: pep8 (E225)
---

diff --git a/misoclib/com/spi/__init__.py b/misoclib/com/spi/__init__.py
index 058cf1e3..a78a6db4 100644
--- a/misoclib/com/spi/__init__.py
+++ b/misoclib/com/spi/__init__.py
@@ -48,9 +48,9 @@ class SPIMaster(Module, AutoCSR):
             )
         ]
 
-        self.comb +=[
-            set_clk.eq(i==div//2-1),
-            clr_clk.eq(i==div-1)
+        self.comb += [
+            set_clk.eq(i == (div//2-1)),
+            clr_clk.eq(i == (div-1))
         ]
 
         # fsm
diff --git a/misoclib/mem/sdram/phy/initsequence.py b/misoclib/mem/sdram/phy/initsequence.py
index 9aede1ed..1a4ffea0 100644
--- a/misoclib/mem/sdram/phy/initsequence.py
+++ b/misoclib/mem/sdram/phy/initsequence.py
@@ -31,7 +31,7 @@ static void command_p{n}(int cmd)
 #define command_prd(X) command_p{rdphase}(X)
 #define command_pwr(X) command_p{wrphase}(X)
 """.format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
-    r +="\n"
+    r += "\n"
 
     #
     # sdrrd/sdrwr functions utilities
@@ -54,7 +54,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
     {sdram_dfii_pix_rddata_addr}
 }};
 """.format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
-    r +="\n"
+    r += "\n"
 
     # init sequence
     cmds = {
diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py
index c270305a..86208d5f 100644
--- a/misoclib/mem/sdram/phy/s6ddrphy.py
+++ b/misoclib/mem/sdram/phy/s6ddrphy.py
@@ -87,7 +87,7 @@ class S6DDRPHY(Module):
         # register dfi cmds on half_rate clk
         r_dfi = Array(Record(phase_cmd_description(addressbits, bankbits)) for i in range(nphases))
         for n, phase in enumerate(self.dfi.phases):
-            sd_sdram_half +=[
+            sd_sdram_half += [
                 r_dfi[n].address.eq(phase.address),
                 r_dfi[n].bank.eq(phase.bank),
                 r_dfi[n].cs_n.eq(phase.cs_n),
diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 2977bd05..4ef8a6f3 100644
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -39,8 +39,8 @@ class SDRAMSoC(SoC):
 
         dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
         sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
-        main_ram_size = 2**(phy.module.geom_settings.bankbits+
-                            phy.module.geom_settings.rowbits+
+        main_ram_size = 2**(phy.module.geom_settings.bankbits +
+                            phy.module.geom_settings.rowbits +
                             phy.module.geom_settings.colbits)*sdram_width//8
         # XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
         main_ram_size = min(main_ram_size, 256*1024*1024)