From: lkcl <lkcl@web>
Date: Sun, 2 Oct 2022 14:13:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~248
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3cdd466109eb4cf13cc6b89ea307857d26dff00;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index a51e4c387..266924467 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -26,10 +26,10 @@ Dynamic SIMD ALUs for maximum performance and effectiveness.
 # Analysis
 
 Covered in [[biginteger/analysis]] the summary is that standard `adde`
-is sufficient for SVP64 Vectorisation of big-integer addition (and subfe
+is sufficient for SVP64 Vectorisation of big-integer addition (and `subfe`
 for subtraction) but that big-integer shift, multiply and divide require an
-extra 3-in 2-out instructions, similar to Intel's `mulx` and
-`idiv`, to be efficient.
+extra 3-in 2-out instructions, similar to Intel's `shld`, `shrd`,
+`mulx` and `idiv`, to be efficient.
 The same instruction (`maddedu`) is used for both because 'maddedu''s primary
 purpose is to perform a fused 64-bit scalar multiply with a large vector,
 where that result is Big-Added for Big-Multiply, but Big-Subtracted for