From: clairexen <claire@symbioticeda.com>
Date: Thu, 16 Jul 2020 16:30:50 +0000 (+0200)
Subject: Merge pull request #2273 from whitequark/write-verilog-always-star-initial
X-Git-Tag: working-ls180~375
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af;p=yosys.git

Merge pull request #2273 from whitequark/write-verilog-always-star-initial

verilog_backend: in non-SV mode, add a trigger for `always @*`
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f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af