From: Clifford Wolf Date: Sat, 20 Oct 2018 21:28:09 +0000 (+0200) Subject: Merge pull request #674 from rubund/feature/svinterface_at_top X-Git-Tag: yosys-0.9~434 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3de732fb4c85c02b64822c0c557a25b158e80ee;p=yosys.git Merge pull request #674 from rubund/feature/svinterface_at_top Support for SystemVerilog interfaces as ports in the top level module + test case --- f3de732fb4c85c02b64822c0c557a25b158e80ee