From: Gabe Black <gabeblack@google.com>
Date: Sat, 13 Oct 2018 00:48:48 +0000 (-0700)
Subject: sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.
X-Git-Tag: v19.0.0.0~1433
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3e17ca77a167ece1972ba73af1c63a85acf9ee8;p=gem5.git

sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.

These types aren't used by the ISA itself since they're defined to be
particular primitive types in the ISA description. This just affects
code outside of the ISA which work with those types of registers.

Change-Id: I4f62ab8fe04184cc23845090c82b250145a71747
Reviewed-on: https://gem5-review.googlesource.com/c/13616
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index a7f4d2a15..b5acaeff1 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -47,8 +47,8 @@ using SparcISAInst::MaxMiscDestRegs;
 
 typedef uint64_t IntReg;
 typedef uint64_t MiscReg;
-typedef float FloatReg;
-typedef uint32_t FloatRegBits;
+typedef double FloatReg;
+typedef uint64_t FloatRegBits;
 
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;