From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 20 Jul 2020 14:05:44 +0000 (+0200)
Subject: Add simple test for DQSPattern
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f3e1bafba499b29896db2919c8bc46e5935381b8;p=gram.git

Add simple test for DQSPattern
---

diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index 10e6159..bfc1447 100644
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -1 +1,30 @@
-import unittest
+from nmigen import *
+from nmigen.hdl.ast import Past
+
+from gram.common import DQSPattern
+from utils import *
+
+class DQSPatternTestCase(FHDLTestCase):
+    def test_async(self):
+        m = Module()
+        m.d.sync += Signal().eq(0) # Workaround for nMigen#417
+        m.submodules.dut = dut = DQSPattern(register=False)
+
+        def process():
+            yield dut.preamble.eq(1) # Preamble=1, Postamble=0
+            yield
+            self.assertEqual((yield dut.o), 0b00010101)
+
+            yield dut.postamble.eq(1) # Preamble=1, Postamble=1
+            yield
+            self.assertEqual((yield dut.o), 0b00010101)
+
+            yield dut.preamble.eq(0) # Preamble=0, Postamble=1
+            yield
+            self.assertEqual((yield dut.o), 0b01010100)
+
+            yield dut.postamble.eq(0) # Preamble=1, Postamble=1
+            yield
+            self.assertEqual((yield dut.o), 0b01010101)
+
+        runSimulation(m, process, "test_dqspattern_async.vcd")